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msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 msp430f552x, msp430f551x mixed-signal microcontrollers 1 device overview 1.1 features 1 ? low-frequency trimmed internal reference ? low supply voltage range: source (refo) 3.6 v down to 1.8 v ? 32-khz watch crystals (xt1) ? ultra-low power consumption ? high-frequency crystals up to 32 mhz (xt2) ? active mode (am): ? 16-bit timer ta0, timer_a with five ? all system clocks active: capture/compare registers ? 290 a/mhz at 8 mhz, 3.0 v, flash ? 16-bit timer ta1, timer_a with three program execution (typical) capture/compare registers ? 150 a/mhz at 8 mhz, 3.0 v, ram ? 16-bit timer ta2, timer_a with three program execution (typical) capture/compare registers ? standby mode (lpm3): ? 16-bit timer tb0, timer_b with seven ? real-time clock (rtc) with crystal, capture/compare shadow registers watchdog, and supply supervisor ? two universal serial communication interfaces operational, full ram retention, fast wake ? usci_a0 and usci_a1 each support: up: ? enhanced uart supports automatic baud- ? 1.9 a at 2.2 v, 2.1 a at 3.0 v (typical) rate detection ? low-power oscillator (vlo), general- ? irda encoder and decoder purpose counter, watchdog, and supply supervisor operational, full ram retention, ? synchronous spi fast wake up: ? usci_b0 and usci_b1 each support: ? 1.4 a at 3.0 v (typical) ? i 2 c ? off mode (lpm4): ? synchronous spi ? full ram retention, supply supervisor ? full-speed universal serial bus (usb) operational, fast wake up: ? integrated usb-phy ? 1.1 a at 3.0 v (typical) ? integrated 3.3-v and 1.8-v usb power system ? shutdown mode (lpm4.5): ? integrated usb-pll ? 0.18 a at 3.0 v (typical) ? eight input and eight output endpoints ? wake up from standby mode in 3.5 s (typical) ? 12-bit analog-to-digital converter (adc) ? 16-bit risc architecture, extended memory, up to (msp430f552x only) with internal reference, 25-mhz system clock sample-and-hold, and autoscan feature ? flexible power management system ? comparator ? fully integrated ldo with programmable ? hardware multiplier supports 32-bit operations regulated core supply voltage ? serial onboard programming, no external ? supply voltage supervision, monitoring, and programming voltage needed brownout ? three-channel internal dma ? unified clock system ? basic timer with rtc feature ? fll control loop for frequency stabilization ? section 3 summarizes available family members ? low-power low-frequency internal clock ? for complete module descriptions, see the source (vlo) msp430x5xx and msp430x6xx family user's guide ( slau208 ) 1.2 applications ? analog and digital sensor systems ? connection to usb hosts ? data loggers 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community referencedesign
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 1.3 description the ti msp430 ? family of ultra-low-power microcontrollers consists of several devices featuring peripheral sets targeted for a variety of applications. the architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. the microcontroller features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that contribute to maximum code efficiency. the digitally controlled oscillator (dco) allows the devices to wake up from low-power modes to active mode in 3.5 s (typical). the msp430f5529, msp430f5527, msp430f5525, and msp430f5521 microcontrollers have integrated usb and phy supporting usb 2.0, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (adc), two universal serial communication interfaces (usci), a hardware multiplier, dma, a real-time clock (rtc) module with alarm capabilities, and 63 i/o pins. the msp430f5528, msp430f5526, msp430f5524, and msp430f5522 microcontrollers include all of these peripherals but have 47 i/o pins. the msp430f5519, msp430f5517, and msp430f5515 microcontrollers have integrated usb and phy supporting usb 2.0, four 16-bit timers, two universal serial communication interfaces (usci), a hardware multiplier, dma, an rtc module with alarm capabilities, and 63 i/o pins. the msp430f5514 and msp430ff5513 microcontrollers include all of these peripherals but have 47 i/o pins. typical applications include analog and digital sensor systems, data loggers, and others that require connectivity to various usb hosts. device information (1) part number package body size (2) msp430f5529pn lqfp (80) 12 mm 12 mm msp430f5528rgc vqfn (64) 9 mm 9 mm msp430f5528yff dsbga (64) 3.5 mm 3.5 mm msp430f5528zqe microstar junior ? bga (80) 5 mm 5 mm (1) for the most current part, package, and ordering information for all available devices, see the package option addendum in section 8 , or see the ti website at www.ti.com . (2) the sizes shown here are approximations. for the package dimensions with tolerances, see the mechanical data in section 8 . 2 device overview copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 1.4 functional block diagrams figure 1-1 shows the functional block diagram for the msp430f5529, msp430f5527, msp430f5525, and msp430f5521 devices in the pn package. figure 1-1. functional block diagram ? msp430f5529ipn, msp430f5527ipn, msp430f5525ipn, msp430f5521ipn figure 1-2 shows the functional block diagram for the msp430f5528, msp430f5526, msp430f5524, and msp430f5522 devices in the rgc and zqe packages and for the msp430f5528, msp430f5526, and msp430f5524 devices in the yff package. figure 1-2. functional block diagram ? msp430f5528irgc, msp430f5526irgc, msp430f5524irgc, msp430f5522irgc msp430f5528izqe, msp430f5526izqe, msp430f5524izqe, msp430f5522izqe msp430f5528iyff, msp430f5526iyff, msp430f5524iyff copyright ? 2009 ? 2015, texas instruments incorporated device overview 3 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 unified clock system 128kb 96kb64kb 32kb flash 8kb+2kb6kb+2kb 4kb+2kb ram mclk aclk smclk i/o ports p1/p2 28 i/os interrupt & wakeup pa 116 i/os cpuxv2 and working registers eem (l: 8+2) xin xout jtag/ interface sbw pa pb pc dma 3 channel xt2in xt out2 power management ldo svm/ brownout svs sys watchdog port map control (p4) i/o ports p3/p4 15 i/os1 pb 113 i/os 8 i/os i/o ports p5/p6 16 i/os pc 114 i/os 18 i/os full-speed usb usb-phy usb-ldo usb-pll mpy32 ta0 timer_a 5 cc registers ta1 timer_a 3 cc registers tb0 timer_b 7 cc registers rtc_a crc16 usci0,1 usci_ax: uart, irda, spi usci_bx: spi, i2c adc12_a 200 ksps 12 channels (10 ext/2 int) autoscan 12 bit dvcc dvss avcc avss p1.x p2.x p3.x p4.x p5.x p6.x dp,dm,pur rst/nmi ta2 timer_a 3 cc registers ref vcore mabmdb comp_b 8 channels unified clock system 128kb 96kb64kb 32kb flash 8kb+2kb6kb+2kb 4kb+2kb ram mclk aclk smclk i/o ports p1/p2 28 i/os interrupt & wakeup pa 116 i/os cpuxv2 and working registers eem (l: 8+2) xin xout jtag/ interface sbw pa pb pc pd dma 3 channel xt2in xt out2 power management ldo svm/ brownout svs sys watchdog port map control (p4) i/o ports p3/p4 28 i/os pb 116 i/os i/o ports p5/p6 28 i/os pc 116 i/os i/o ports p7/p8 18 i/os1 pd 111 i/os 3 i/os full-speed usb usb-phy usb-ldo usb-pll mpy32 ta0 timer_a 5 cc registers ta1 timer_a 3 cc registers tb0 timer_b 7 cc registers rtc_a crc16 usci0,1 usci_ax: uart, irda, spi usci_bx: spi, i2c adc12_a 200 ksps 16 channels (14 ext/2 int) autoscan 12 bit dvcc dvss avcc avss p1.x p2.x p3.x p4.x p5.x p6.x dp,dm,pur rst/nmi ta2 timer_a 3 cc registers ref vcore mabmdb p7.x p8.x comp_b 12 channels
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 1-3 shows the functional block diagram for the msp430f5519, msp430f5517, and msp430f5515 devices in the pn package. figure 1-3. functional block diagram ? msp430f5519ipn, msp430f5517ipn, msp430f5515ipn figure 1-4 shows the functional block diagram for the msp430f5514 and msp430f5513 devices in the rgc and zqe packages. figure 1-4. functional block diagram ? msp430f5514irgc, msp430f5513irgc, msp430f5514izqe, msp430f5513izqe 4 device overview copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 unified clock system 64kb32kb flash 4kb+2kb ram mclk aclk smclk i/o ports p1/p2 28 i/os interrupt & wakeup pa 116 i/os cpuxv2 and working registers eem (l: 8+2) xin xout jtag/ sbw interface pa pb pc dma 3 channel xt2in xt2out power management ldo svm/svs brownout sys watchdog port map control (p4) i/o ports p3/p4 15 i/os1 pb 113 i/os 8 i/os i/o ports p5/p6 16 i/os pc 114 i/os 18 i/os full-speed usb usb-phy usb-ldo usb-pll mpy32 ta0 timer_a 5 cc registers ta1 timer_a 3 cc registers tb0 timer_b 7 cc registers rtc_a crc16 usci0,1 usci_ax: uart, irda, spi usci_bx: spi, i2c dvcc dvss avcc avss p1.x p2.x p3.x p4.x p5.x p6.x dp,dm,pur rst/nmi ta2 timer_a 3 cc registers comp_b 8 channels vcore mabmdb ref unified clock system 128kb 96kb64kb flash 4kb+2kb ram mclk aclk smclk i/o ports p1/p2 28 i/os interrupt & wakeup pa 116 i/os cpuxv2 and working registers eem (l: 8+2) xin xout jtag/ sbw interface pa pb pc pd dma 3 channel xt2in xt2out power management ldo svm/svs brownout sys watchdog port map control (p4) i/o ports p3/p4 28 i/os pb 116 i/os i/o ports p5/p6 28 i/os pc 116 i/os i/o ports p7/p8 18 i/os1 pd 111 i/os 3 i/os full-speed usb usb-phy usb-ldo usb-pll mpy32 ta0 timer_a 5 cc registers ta1 timer_a 3 cc registers tb0 timer_b 7 cc registers rtc_a crc16 usci0,1 usci_ax: uart, irda, spi usci_bx: spi, i2c dvcc dvss avcc avss p1.x p2.x p3.x p4.x p5.x p6.x dp,dm,pur rst/nmi ta2 timer_a 3 cc registers comp_b 12 channels vcore mabmdb p7.x p8.x ref
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table of contents 1 device overview ......................................... 1 5.24 pmm, svs low side ................................ 33 1.1 features .............................................. 1 5.25 pmm, svm low side ............................... 33 5.26 wake-up times from low-power modes and 1.2 applications ........................................... 1 reset ................................................ 34 1.3 description ............................................ 2 5.27 timer_a ............................................. 34 1.4 functional block diagrams ........................... 3 5.28 timer_b ............................................. 34 2 revision history ......................................... 6 5.29 usci (uart mode) clock frequency .............. 35 3 device comparison ..................................... 7 5.30 usci (uart mode) ................................. 35 4 terminal configuration and functions .............. 8 5.31 usci (spi master mode) clock frequency ......... 35 4.1 pin diagrams ......................................... 8 5.32 usci (spi master mode) ............................ 35 4.2 signal descriptions .................................. 14 5.33 usci (spi slave mode) ............................. 37 5 specifications ........................................... 19 5.34 usci (i 2 c mode) .................................... 39 5.1 absolute maximum ratings ........................ 19 5.35 12-bit adc, power supply and input range 5.2 esd ratings ........................................ 19 conditions ........................................... 40 5.3 recommended operating conditions ............... 19 5.36 12-bit adc, timing parameters .................... 40 5.4 active mode supply current into v cc excluding 5.37 12-bit adc, linearity parameters using an external external current ..................................... 21 reference voltage or avcc as reference voltage 41 5.5 low-power mode supply currents (into v cc ) 5.38 12-bit adc, linearity parameters using the internal excluding external current .......................... 22 reference voltage .................................. 41 5.6 thermal characteristics ............................. 23 5.39 12-bit adc, temperature sensor and built-in v mid 42 5.7 schmitt-trigger inputs ? general-purpose i/o 5.40 ref, external reference ........................... 43 (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to 5.41 ref, built-in reference ............................. 43 p8.2, pj.0 to pj.3, rst/nmi) ....................... 24 5.42 comparator_b ....................................... 45 5.8 inputs ? ports p1 and p2 5.43 ports pu.0 and pu.1 ................................ 45 (p1.0 to p1.7, p2.0 to p2.7) ......................... 24 5.44 usb output ports dp and dm ...................... 47 5.9 leakage current ? general-purpose i/o 5.45 usb input ports dp and dm ........................ 47 (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to 5.46 usb-pwr (usb power system) ................... 48 p8.2, pj.0 to pj.3, rst/nmi) ....................... 24 5.47 usb-pll (usb phase locked loop) ............... 48 5.10 outputs ? general-purpose i/o (full drive strength) 5.48 flash memory ....................................... 49 (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to 5.49 jtag and spy-bi-wire interface .................... 49 p8.2, pj.0 to pj.3) .................................. 24 6 detailed description ................................... 50 5.11 outputs ? general-purpose i/o (reduced drive 6.1 cpu (link to user ' s guide) ......................... 50 strength) 6.2 operating modes .................................... 51 (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to 6.3 interrupt vector addresses .......................... 52 p8.2, pj.0 to pj.3) .................................. 25 6.4 memory organization ............................... 53 5.12 output frequency ? general-purpose i/o 6.5 bootstrap loader (bsl) ............................. 54 (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) 6.6 jtag operation ..................................... 55 (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3) .................................. 25 6.7 flash memory (link to user ' s guide) ............... 56 5.13 typical characteristics ? outputs, reduced drive 6.8 ram (link to user ' s guide) ......................... 56 strength (pxds.y = 0) ............................... 26 6.9 peripherals .......................................... 56 5.14 typical characteristics ? outputs, full drive 6.10 input/output schematics ............................ 81 strength (pxds.y = 1) ............................... 27 6.11 device descriptors (tlv) .......................... 103 5.15 crystal oscillator, xt1, low-frequency mode ..... 28 7 device and documentation support .............. 109 5.16 crystal oscillator, xt2 .............................. 29 7.1 device support ..................................... 109 5.17 internal very-low-power low-frequency oscillator 7.2 documentation support ............................ 112 (vlo) ................................................ 30 5.18 internal reference, low-frequency oscillator 7.3 related links ...................................... 113 (refo) .............................................. 30 7.4 community resources ............................. 113 5.19 dco frequency ..................................... 31 7.5 trademarks ........................................ 113 5.20 pmm, brown-out reset (bor) ..................... 32 7.6 electrostatic discharge caution ................... 113 5.21 pmm, core voltage ................................. 32 7.7 glossary ............................................ 113 5.22 pmm, svs high side ............................... 32 8 mechanical, packaging, and orderable 5.23 pmm, svm high side ............................... 33 information ............................................. 114 copyright ? 2009 ? 2015, texas instruments incorporated table of contents 5 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 2 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision l (june 2013) to revision m page ? formatting and organization changes throughout, including addition of section numbering ............................... 1 ? added device information table .................................................................................................... 2 ? added section 1.4 and moved all functional block diagrams to it .............................................................. 3 ? added section 3 and moved family members table to it ....................................................................... 7 ? added section 5 and moved all electrical specifications to it ................................................................. 19 ? added section 5.2 , esd ratings .................................................................................................. 19 ? moved section 5.6 , thermal characteristics .................................................................................... 23 ? changed the typ value of c l,eff with test conditions of " xts = 0, xcapx = 0 " from 2 pf to 1 pf ..................... 28 ? corrected mrg0 and mrg1 bit names in f mclk,mrg parameter description ................................................. 49 ? corrected spelling of nmiifg in table 6-9 , system module interrupt vector registers ................................... 60 ? corrected register names (added " usb " prefix as necessary) in table 6-45 , usb control registers .................. 80 ? changed p5.3 schematic (added p5sel.2 and xt2bypass inputs, and gate, and or gate after p5sel.3) ....... 89 ? changed p5sel.3 column from x to 0 for " p5.3 (i/o) " rows .................................................................. 89 ? changed p5.5 schematic (change input from p5sel.5 to p5sel.4 and added p5sel.5 input and the following or gate) .............................................................................................................................. 91 ? changed p5sel.5 column from x to 0 for " p5.5 (i/o) " rows .................................................................. 91 ? added section 7 and moved tools support , device nomenclature , esd caution , and trademarks sections to it .. 109 ? added section 8 , mechanical, packaging, and orderable information ..................................................... 114 6 revision history copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 3 device comparison table 3-1 summarizes the available family members. table 3-1. family members (1) (2) usci flash sram adc12_a comp_b channel a: channel b: device timer_a (4) timer_b (5) i/o package (kb) (kb) (3) (ch) (ch) uart, irda, spi, i 2 c spi msp430f5529 128 8 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 pn 64 rgc, msp430f5528 128 8 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 yff, 80 zqe msp430f5527 96 6 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 pn 64 rgc, msp430f5526 96 6 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 yff, 80 zqe msp430f5525 64 4 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 pn 64 rgc, msp430f5524 64 4 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 yff, 80 zqe 64 rgc, msp430f5522 32 8 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 80 zqe msp430f5521 32 6 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 pn msp430f5519 128 8 + 2 5, 3, 3 7 2 2 ? 12 63 80 pn msp430f5517 96 6 + 2 5, 3, 3 7 2 2 ? 12 63 80 pn msp430f5515 64 4 + 2 5, 3, 3 7 2 2 ? 12 63 80 pn 64 rgc, msp430f5514 64 4 + 2 5, 3, 3 7 2 2 ? 8 47 80 zqe 64 rgc, msp430f5513 32 4 + 2 5, 3, 3 7 2 2 ? 8 47 80 zqe (1) for the most current part, package, and ordering information for all available devices, see the package option addendum in section 8 , or see the ti website at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging . (3) the additional 2kb usb sram that is listed can be used as general-purpose sram when usb is not in use. (4) each number in the sequence represents an instantiation of timer_a with its associated number of capture/compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_a, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and pwm output generators, respectively. (5) each number in the sequence represents an instantiation of timer_b with its associated number of capture/compare registers and pwm output generators available. for example, a number sequence of 3, 5 would represent two instantiations of timer_b, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and pwm output generators, respectively. copyright ? 2009 ? 2015, texas instruments incorporated device comparison 7 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 4 terminal configuration and functions 4.1 pin diagrams figure 4-1 shows the pinout for the msp430f5529, msp430f5527, msp430f5525, and msp430f5521 devices in the pn package. figure 4-1. pin designation ? msp430f5529ipn, msp430f5527ipn, msp430f5525ipn, msp430f5521ipn (top view) 8 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 6059 58 57 56 5554 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p6.4/cb4/a4 p6.5/cb5/a5 p6.6/cb6/a6 p6.7/cb7/a7 p7.0/cb8/a12 p7.1/cb9/a13 p7.2/cb10/a14 p7.3/cb11/a15 p5.0/a8/vref+/veref+ p5.1/a9/vref?/veref? avcc1 avss1 p5.4/xin p5.5/xout p1.0/ta0clk/aclk p1.1/ta0.0 p1.2/ta0.1 p1.3/ta0.2 dvcc2dvss2 vcore msp430f5529msp430f5527 msp430f5525 msp430f5521 rst/nmi/sbwtdio pj.3/tckpj.2/tms pj.1/tdi/tclk pj.0/tdo test/sbwtck p5.3/xt2out p5.2/xt2in avss2 v18 vusb vbus pu.1/dm pur pu.0/dp vssu p1.6/ta1clk/cbout p1.5/ta0.4 p1.7/ta1.0 p2.2/ta2clk/smclk p2.0/ta1.1 p2.3/ta2.0 p2.4/ta2.1 p2.5/ta2.2 p2.6/rtcclk/dmae0 p2.7/ucb0ste/uca0clk p3.0/ucb0simo/ucb0sda p3.1/ucb0somi/ucb0scl p3.2/ucb0clk/uca0ste p3.3/uca0txd/uca0simo p3.4/uca0rxd/uca0somi p7.4/tb0.2 p7.5/tb0.3 dvss1 dvcc1 p1.4/ta0.3 p2.1/ta1.2 p3.6/tb0.6 p3.7/tb0outh/svmout p4.2/pm_ucb1somi/pm_ucb1sclp4.1/pm_ucb1simo/pm_ucb1sda p4.0/pm_ucb1ste/pm_uca1clk p4.5/pm_uca1rxd/pm_uca1somip4.4/pm_uca1txd/pm_uca1simo p4.3/pm_ucb1clk/pm_uca1ste p4.6/pm_none p4.7/pm_none p5.6/tb0.0 p5.7/tb0.1 p7.6/tb0.4 p7.7/tb0clk/mclk p6.3/cb3/a3p6.2/cb2/a2 p6.1/cb1/a1 p6.0/cb0/a0 p3.5/tb0.5 p8.0 p8.1 p8.2
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 figure 4-2 shows the pinout for the msp430f5528, msp430f5526, msp430f5524, and msp430f5522 devices in the rgc package. note: ti recommends connecting the exposed thermal pad to v ss . figure 4-2. pin designation ? msp430f5528irgc, msp430f5526irgc, msp430f5524irgc, msp430f5522irgc (top view) copyright ? 2009 ? 2015, texas instruments incorporated terminal configuration and functions 9 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 msp430f5528msp430f5526 msp430f5524 msp430f5522 p6.3/cb3/a3 p6.2/cb2/a2 p6.1/cb1/a1 p6.0/cb0/a0 p1.6/ta1clk/cbout p1.7/ta1.0 p2.0/ta1.1 p2.1/ta1.2 p2.2/ta2clk/smclk p2.3/ta2.0 p2.4/ta2.1 p2.5/ta2.2 p2.6/rtcclk/dmae0 p2.7/ucb0ste/uca0clk p3.0/ucb0simo/ucb0sda p3.1/ucb0somi/ucb0scl p3.2/ucb0clk/uca0ste p6.4/cb4/a4 p6.5/cb5/a5 p6.6/cb6/a6 p6.7/cb7/a7 p5.0/a8/vref+/veref+ p5.1/a9/vref?/veref? avcc1 avss1 p5.4/xin p5.5/xout p1.0/ta0clk/aclk p1.1/ta0.0 p1.2/ta0.1 p1.3/ta0.2 dvss1 dvcc1 dvcc2dvss2 p4.2/pm_ucb1somi/pm_ucb1sclp4.1/pm_ucb1simo/pm_ucb1sda p4.0/pm_ucb1ste/pm_uca1clk p4.5/pm_uca1rxd/pm_uca1somip4.4/pm_uca1txd/pm_uca1simo p4.3/pm_ucb1clk/pm_uca1ste p3.3/uca0txd/uca0simo p3.4/uca0rxd/uca0somi p4.6/pm_none p4.7/pm_none 17 64 18 63 19 62 20 61 21 60 22 59 29 52 30 51 31 50 32 49 23 58 24 57 25 56 26 55 27 54 28 53 33 16 34 15 35 14 36 13 37 12 38 11 45 4 46 3 47 2 48 1 39 10 40 9 41 8 42 7 43 6 44 5 p1.4/ta0.3 p1.5/ta0.4 rst/nmi/sbwtdio pj.3/tckpj.2/tms pj.1/tdi/tclk pj.0/tdo test/sbwtck p5.3/xt2out p5.2/xt2in avss2 v18 vusb vbus pu.1/dm pur pu.0/dp vssu vcore
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 4-3 shows the pinout for the msp430f5519, msp430f5517, and msp430f5515 devices in the pn package. figure 4-3. pin designation ? msp430f5519ipn, msp430f5517ipn, msp430f5515ipn (top view) 10 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 6059 58 57 56 5554 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 p6.4/cb4 p6.5/cb5 p6.6/cb6 p6.7/cb7 p7.0/cb8 p7.1/cb9 p7.2/cb10 p7.3/cb11 p5.0p5.1 avcc1 avss1 p5.4/xin p5.5/xout p1.0/ta0clk/aclk p1.1/ta0.0 p1.2/ta0.1 p1.3/ta0.2 dvcc2dvss2 vcore msp430f5519msp430f5517 msp430f5515 rst/nmi/sbwtdio pj.3/tckpj.2/tms pj.1/tdi/tclk pj.0/tdo test/sbwtck p5.3/xt2out p5.2/xt2in avss2 v18 vusb vbus pu.1/dm pur pu.0/dp vssu p1.6/ta1clk/cbout p1.5/ta0.4 p1.7/ta1.0 p2.2/ta2clk/smclk p2.0/ta1.1 p2.3/ta2.0 p2.4/ta2.1 p2.5/ta2.2 p2.6/rtcclk/dmae0 p2.7/ucb0ste/uca0clk p3.0/ucb0simo/ucb0sda p3.1/ucb0somi/ucb0scl p3.2/ucb0clk/uca0ste p3.3/uca0txd/uca0simo p3.4/uca0rxd/uca0somi p7.4/tb0.2 p7.5/tb0.3 dvss1 dvcc1 p1.4/ta0.3 p2.1/ta1.2 p3.6/tb0.6 p3.7/tb0outh/svmout p4.2/pm_ucb1somi/pm_ucb1sclp4.1/pm_ucb1simo/pm_ucb1sda p4.0/pm_ucb1ste/pm_uca1clk p4.5/pm_uca1rxd/pm_uca1somip4.4/pm_uca1txd/pm_uca1simo p4.3/pm_ucb1clk/pm_uca1ste p4.6/pm_none p4.7/pm_none p5.6/tb0.0 p5.7/tb0.1 p7.6/tb0.4 p7.7/tb0clk/mclk p6.3/cb3p6.2/cb2 p6.1/cb1 p6.0/cb0 p3.5/tb0.5 p8.0p8.1 p8.2
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 figure 4-4 shows the pinout for the msp430f5514 and msp430f5513 devices in the rgc package. note: ti recommends connecting the exposed thermal pad to v ss . figure 4-4. pin designation ? msp430f5514irgc, msp430f5513irgc (top view) copyright ? 2009 ? 2015, texas instruments incorporated terminal configuration and functions 11 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 msp430f5514msp430f5513 p6.3/cb3 p6.2/cb2 p6.1/cb1 p6.0/cb0 p1.6/ta1clk/cbout p1.7/ta1.0 p2.0/ta1.1 p2.1/ta1.2 p2.2/ta2clk/smclk p2.3/ta2.0 p2.4/ta2.1 p2.5/ta2.2 p2.6/rtcclk/dmae0 p2.7/ucb0ste/uca0clk p3.0/ucb0simo/ucb0sda p3.1/ucb0somi/ucb0scl p3.2/ucb0clk/uca0ste p6.4/cb4 p6.5/cb5 p6.6/cb6 p6.7/cb7 p5.0p5.1 avcc1 avss1 p5.4/xin p5.5/xout p1.0/ta0clk/aclk p1.1/ta0.0 p1.2/ta0.1 p1.3/ta0.2 dvss1 dvcc1 dvcc2dvss2 p4.2/pm_ucb1somi/pm_ucb1sclp4.1/pm_ucb1simo/pm_ucb1sda p4.0/pm_ucb1ste/pm_uca1clk p4.5/pm_uca1rxd/pm_uca1somip4.4/pm_uca1txd/pm_uca1simo p4.3/pm_ucb1clk/pm_uca1ste p3.3/uca0txd/uca0simo p3.4/uca0rxd/uca0somi p4.6/pm_none p4.7/pm_none 17 64 18 63 19 62 20 61 21 60 22 59 29 52 30 51 31 50 32 49 23 58 24 57 25 56 26 55 27 54 28 53 33 16 34 15 35 14 36 13 37 12 38 11 45 4 46 3 47 2 48 1 39 10 40 9 41 8 42 7 43 6 44 5 p1.4/ta0.3 p1.5/ta0.4 rst/nmi/sbwtdio pj.3/tckpj.2/tms pj.1/tdi/tclk pj.0/tdo test/sbwtck p5.3/xt2out p5.2/xt2in avss2 v18 vusb vbus pu.1/dm pur pu.0/dp vssu vcore
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 4-5 shows the pinout for the msp430f5528, msp430f5526, msp430f5524, msp430f5522, msp430f5514, and msp430f5513 devices in the zqe package. figure 4-5. pin designation ? msp430f5528izqe, msp430f5526izqe, msp430f5524izqe, msp430f5522izqe, msp430f5514izqe, msp430f5513izqe (top view) 12 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 a1 a2 a3 a4 a5 a6 a7 a8 a9 b1 b2 b3 b4 b5 b6 b7 b8 b9 c1 c2 d1 d2 d4 d5 d6 d7 d8 d9 e1 e2 e4 e5 e6 e7 e8 e9 f1 f2 f4 f5 f8 f9 g1 g2 g4 g5 g8 g9 j1 j2 j4 j5 j6 j7 j8 j9 h1 h2 h4 h5 h6 h7 h8 h9 c4 c5 c6 c7 c8 c9 d3 e3 f3 g3 j3 h3 f6 g6 f7 g7 p6.0 rst/nmi pj.2 test avss2 vusb vbus pu.1 pu.0 p6.2 p6.1 pj.3 p5.3 p5.2 v18 pur vssu vssu p6.4 p6.3 p6.6 p6.5 reserved reserved reserved p4.4 p4.3 p4.2 p5.0 p5.1 reserved reserved reserved p4.1 p4.0 dvcc2 p5.4 avcc1 reserved reserved reserved dvss2 p5.5 avss1 p1.3 p1.6 p3.2 p3.3 dvss1 vcore p1.5 p2.0 p2.2 p2.4 p2.5 p2.6 dvcc1 p1.0 p1.4 p1.7 p2.3 p2.7 p3.0 p3.1 pj.1 pj.0 reserved p4.7 p4.6 p4.5 p6.7 reservedreserved reserved p1.2 p1.1 reserved p2.1 reserved p3.4
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 figure 4-6 shows the pinout for the msp430f5528, msp430f5526, and msp430f5524 devices in the yff package. figure 4-6. pin designation ? msp430f5528iyff, msp430f5526iyff, msp430f5524iyff copyright ? 2009 ? 2015, texas instruments incorporated terminal configuration and functions 13 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 d1 d2 d4 d5 d6 d7 d8 e1 e2 e4 e5 e6 e7 e8 f1 f2 f4 f5 f8 g1 g2 g4 g5 g8 h1 h2 h4 h5 h6 h7 h8 c4 c5 c6 c7 c8 d3 e3 f3 g3 h3 f6 g6 f7 g7 c3 p6.2 p6.6 avcc1 avss1 p5.4 p5.5 dvcc1 dvss1 p6.0 p6.4 p6.5 p5.0 p5.1 p1.1 p1.0 vcore pj.2 pj.3 p5.3 avss2 pj.1 rst/nmi p1.5 p1.6 p1.7 p5.2 v18 p4.7 p2.0 p2.3 p2.2 p2.1 vusb vbus p4.3 p4.0 p2.4 pu.1 pur p4.2 p3.4 p3.0 pu.0 vssu p4.1 dvcc2 dvss2 p3.1 p2.7 p6.3 p6.7 p1.2 p1.4 p1.3 pj.0 test p4.6 p4.5 p4.4 p2.6 p3.3 p2.5 p3.2 p6.1 top view ball-side view a1 a2 a3 a4 a5 a6 a7 a8 b1 b2 b3 b4 b5 b6 b7 b8 c1 c2 d1 d2 d4 d5 d6 d7 d8 e1 e2 e4 e5 e6 e7 e8 f1 f2 f4 f5 f8 g1 g2 g4 g5 g8 h1 h2 h4 h5 h6 h7 h8 c4 c5 c6 c7 c8 d3 e3 f3 g3 h3 f6 g6 f7 g7 c3 p6.2 p6.6 avcc1 avss1 p5.4 p5.5 dvcc1 dvss1 p6.0 p6.4 p6.5 p5.0 p5.1 p1.1 p1.0 vcore pj.2 pj.3 p5.3 avss2 pj.1 rst/nmi p1.5 p1.6 p1.7 p5.2 v18 p4.7 p2.0 p2.3 p2.2 p2.1 vusb vbus p4.3 p4.0 p2.4 pu.1 pur p4.2 p3.4 p3.0 pu.0 vssu p4.1 dvcc2 dvss2 p3.1 p2.7 p6.3 p6.7 p1.2 p1.4 p1.3 pj.0 test p4.6 p4.5 p4.4 p2.6 p3.3 p2.5 p3.2 p6.1 d e d e
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 4.2 signal descriptions table 4-1. terminal functions terminal no. i/o (1) description name pn rgc yff zqe general-purpose digital i/o p6.4/cb4/a4 1 5 b2 c1 i/o comparator_b input cb4 analog input a4 ? adc (not available on f551x devices) general-purpose digital i/o p6.5/cb5/a5 2 6 b3 d2 i/o comparator_b input cb5 analog input a5 ? adc (not available on f551x devices) general-purpose digital i/o p6.6/cb6/a6 3 7 a2 d1 i/o comparator_b input cb6 analog input a6 ? adc (not available on f551x devices) general-purpose digital i/o p6.7/cb7/a7 4 8 c5 d3 i/o comparator_b input cb7 analog input a7 ? adc (not available on f551x devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.0/cb8/a12 5 n/a n/a n/a i/o comparator_b input cb8 (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) analog input a12 ? adc (not available on f551x devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.1/cb9/a13 6 n/a n/a n/a i/o comparator_b input cb9 (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) analog input a13 ? adc (not available on f551x devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.2/cb10/a14 7 n/a n/a n/a i/o comparator_b input cb10 (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) analog input a14 ? adc (not available on f551x devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.3/cb11/a15 8 n/a n/a n/a i/o comparator_b input cb11 (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) analog input a15 ? adc (not available on f551x devices) general-purpose digital i/o output of reference voltage to the adc (not available on f551x devices) p5.0/a8/vref+/veref+ 9 9 b4 e1 i/o input for an external reference voltage to the adc (not available on f551x devices) analog input a8 ? adc (not available on f551x devices) general-purpose digital i/o negative terminal for the adc reference voltage for both sources, the internal p5.1/a9/vref-/veref- 10 10 b5 e2 i/o reference voltage, or an external applied reference voltage (not available on f551x devices) analog input a9 ? adc (not available on f551x devices) avcc1 11 11 a3 f2 analog power supply general-purpose digital i/o p5.4/xin 12 12 a5 f1 i/o input terminal for crystal oscillator xt1 general-purpose digital i/o p5.5/xout 13 13 a6 g1 i/o output terminal of crystal oscillator xt1 avss1 14 14 a4 g2 analog ground supply p8.0 15 n/a n/a n/a i/o general-purpose digital i/o p8.1 16 n/a n/a n/a i/o general-purpose digital i/o p8.2 17 n/a n/a n/a i/o general-purpose digital i/o (1) i = input, o = output, n/a = not available 14 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 4-1. terminal functions (continued) terminal no. i/o (1) description name pn rgc yff zqe dvcc1 18 15 a7 h1 digital power supply dvss1 19 16 a8 j1 digital ground supply vcore (2) 20 17 b8 j2 regulated core power supply output (internal use only, no external current loading) general-purpose digital i/o with port interrupt p1.0/ta0clk/aclk 21 18 b7 h2 i/o ta0 clock signal ta0clk input aclk output (divided by 1, 2, 4, 8, 16, or 32) general-purpose digital i/o with port interrupt p1.1/ta0.0 22 19 b6 h3 i/o ta0 ccr0 capture: cci0a input, compare: out0 output bsl transmit output general-purpose digital i/o with port interrupt p1.2/ta0.1 23 20 c6 j3 i/o ta0 ccr1 capture: cci1a input, compare: out1 output bsl receive input general-purpose digital i/o with port interrupt p1.3/ta0.2 24 21 c8 g4 i/o ta0 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o with port interrupt p1.4/ta0.3 25 22 c7 h4 i/o ta0 ccr3 capture: cci3a input compare: out3 output general-purpose digital i/o with port interrupt p1.5/ta0.4 26 23 d6 j4 i/o ta0 ccr4 capture: cci4a input, compare: out4 output general-purpose digital i/o with port interrupt p1.6/ta1clk/cbout 27 24 d7 g5 i/o ta1 clock signal ta1clk input comparator_b output general-purpose digital i/o with port interrupt p1.7/ta1.0 28 25 d8 h5 i/o ta1 ccr0 capture: cci0a input, compare: out0 output general-purpose digital i/o with port interrupt p2.0/ta1.1 29 26 e5 j5 i/o ta1 ccr1 capture: cci1a input, compare: out1 output general-purpose digital i/o with port interrupt p2.1/ta1.2 30 27 e8 g6 i/o ta1 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o with port interrupt p2.2/ta2clk/smclk 31 28 e7 j6 i/o ta2 clock signal ta2clk input smclk output general-purpose digital i/o with port interrupt p2.3/ta2.0 32 29 e6 h6 i/o ta2 ccr0 capture: cci0a input, compare: out0 output general-purpose digital i/o with port interrupt p2.4/ta2.1 33 30 f8 j7 i/o ta2 ccr1 capture: cci1a input, compare: out1 output general-purpose digital i/o with port interrupt p2.5/ta2.2 34 31 f7 j8 i/o ta2 ccr2 capture: cci2a input, compare: out2 output general-purpose digital i/o with port interrupt p2.6/rtcclk/dmae0 35 32 f6 j9 i/o rtc clock output for calibration dma external trigger input general-purpose digital i/o with port interrupt slave transmit enable ? usci_b0 spi mode p2.7/ucb0ste/uca0clk 36 33 h8 h7 i/o clock signal input ? usci_a0 spi slave mode clock signal output ? usci_a0 spi master mode general-purpose digital i/o slave in, master out ? usci_b0 spi mode p3.0/ucb0simo/ucb0sda 37 34 g8 h8 i/o i 2 c data ? usci_b0 i 2 c mode (2) vcore is for internal use only. no external current loading is possible. vcore should only be connected to the recommended capacitor value, c vcore . copyright ? 2009 ? 2015, texas instruments incorporated terminal configuration and functions 15 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 4-1. terminal functions (continued) terminal no. i/o (1) description name pn rgc yff zqe general-purpose digital i/o slave out, master in ? usci_b0 spi mode p3.1/ucb0somi/ucb0scl 38 35 h7 h9 i/o i 2 c clock ? usci_b0 i 2 c mode general-purpose digital i/o clock signal input ? usci_b0 spi slave mode p3.2/ucb0clk/uca0ste 39 36 g7 g8 i/o clock signal output ? usci_b0 spi master mode slave transmit enable ? usci_a0 spi mode general-purpose digital i/o p3.3/uca0txd/uca0simo 40 37 g6 g9 i/o transmit data ? usci_a0 uart mode slave in, master out ? usci_a0 spi mode general-purpose digital i/o p3.4/uca0rxd/uca0somi 41 38 g5 g7 i/o receive data ? usci_a0 uart mode slave out, master in ? usci_a0 spi mode general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p3.5/tb0.5 42 n/a n/a n/a i/o tb0 ccr5 capture: cci5a input, compare: out5 output general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p3.6/tb0.6 43 n/a n/a n/a i/o tb0 ccr6 capture: cci6a input, compare: out6 output general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p3.7/tb0outh/svmout 44 n/a n/a n/a i/o switch all pwm outputs high impedance input ? tb0 (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) svm output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o with reconfigurable port mapping secondary function default mapping: slave transmit enable ? usci_b1 spi mode p4.0/pm_ucb1ste/ 45 41 f5 e8 i/o pm_uca1clk default mapping: clock signal input ? usci_a1 spi slave mode default mapping: clock signal output ? usci_a1 spi master mode general-purpose digital i/o with reconfigurable port mapping secondary function p4.1/pm_ucb1simo/ default mapping: slave in, master out ? usci_b1 spi mode 46 42 h4 e7 i/o pm_ucb1sda default mapping: i 2 c data ? usci_b1 i 2 c mode general-purpose digital i/o with reconfigurable port mapping secondary function p4.2/pm_ucb1somi/ default mapping: slave out, master in ? usci_b1 spi mode 47 43 g4 d9 i/o pm_ucb1scl default mapping: i 2 c clock ? usci_b1 i 2 c mode general-purpose digital i/o with reconfigurable port mapping secondary function default mapping: clock signal input ? usci_b1 spi slave mode p4.3/pm_ucb1clk/ 48 44 f4 d8 i/o pm_uca1ste default mapping: clock signal output ? usci_b1 spi master mode default mapping: slave transmit enable ? usci_a1 spi mode dvss2 49 39 h6 f9 digital ground supply dvcc2 50 40 h5 e9 digital power supply general-purpose digital i/o with reconfigurable port mapping secondary function p4.4/pm_uca1txd/ 51 45 h3 d7 i/o default mapping: transmit data ? usci_a1 uart mode pm_uca1simo default mapping: slave in, master out ? usci_a1 spi mode general-purpose digital i/o with reconfigurable port mapping secondary function p4.5/pm_uca1rxd/ 52 46 g3 c9 i/o default mapping: receive data ? usci_a1 uart mode pm_uca1somi default mapping: slave out, master in ? usci_a1 spi mode general-purpose digital i/o with reconfigurable port mapping secondary function p4.6/pm_none 53 47 f3 c8 i/o default mapping: no secondary function. general-purpose digital i/o with reconfigurable port mapping secondary function p4.7/pm_none 54 48 e4 c7 i/o default mapping: no secondary function. 16 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 4-1. terminal functions (continued) terminal no. i/o (1) description name pn rgc yff zqe general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p5.6/tb0.0 55 n/a n/a n/a i/o tb0 ccr0 capture: cci0a input, compare: out0 output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p5.7/tb0.1 56 n/a n/a n/a i/o tb0 ccr1 capture: cci1a input, compare: out1 output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.4/tb0.2 57 n/a n/a n/a i/o tb0 ccr2 capture: cci2a input, compare: out2 output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.5/tb0.3 58 n/a n/a n/a i/o tb0 ccr3 capture: cci3a input, compare: out3 output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) p7.6/tb0.4 59 n/a n/a n/a i/o tb0 ccr4 capture: cci4a input, compare: out4 output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) general-purpose digital i/o (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) tb0 clock signal tbclk input (not available on f5528, f5526, f5524, f5522, p7.7/tb0clk/mclk 60 n/a n/a n/a i/o f5514, f5513 devices) mclk output (not available on f5528, f5526, f5524, f5522, f5514, f5513 devices) b8, vssu 61 49 h2 usb phy ground supply b9 general-purpose digital i/o. controlled by usb control register pu.0/dp 62 50 h1 a9 i/o usb data terminal dp usb pullup resistor pin (open drain). the voltage level at the pur pin is used to pur 63 51 g2 b7 i/o invoke the default usb bsl. recommended 1-m resistor to ground. see section 6.5.1 for more information. general-purpose digital i/o. controlled by usb control register pu.1/dm 64 52 g1 a8 i/o usb data terminal dm vbus 65 53 f2 a7 usb ldo input (connect to usb power source) vusb 66 54 f1 a6 usb ldo output v18 67 55 e2 b6 usb regulated power (internal use only, no external current loading) avss2 68 56 d2 a5 analog ground supply general-purpose digital i/o p5.2/xt2in 69 57 e1 b5 i/o input terminal for crystal oscillator xt2 general-purpose digital i/o p5.3/xt2out 70 58 d1 b4 i/o output terminal of crystal oscillator xt2 test mode pin ? selects four wire jtag operation test/sbwtck (3) 71 59 e3 a4 i spy-bi-wire input clock when spy-bi-wire operation activated general-purpose digital i/o pj.0/tdo (4) 72 60 d3 c5 i/o jtag test data output port general-purpose digital i/o pj.1/tdi/tclk (4) 73 61 d4 c4 i/o jtag test data input test clock input general-purpose digital i/o pj.2/tms (4) 74 62 c1 a3 i/o jtag test mode select (3) see section 6.5 and section 6.6 for use with bsl and jtag functions. (4) see section 6.6 for use with jtag function. copyright ? 2009 ? 2015, texas instruments incorporated terminal configuration and functions 17 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 4-1. terminal functions (continued) terminal no. i/o (1) description name pn rgc yff zqe general-purpose digital i/o pj.3/tck (4) 75 63 c2 b3 i/o jtag test clock reset input, active low (5) rst/nmi/sbwtdio (3) 76 64 d5 a2 i/o nonmaskable interrupt input spy-bi-wire data input/output when spy-bi-wire operation activated general-purpose digital i/o p6.0/cb0/a0 77 1 b1 a1 i/o comparator_b input cb0 analog input a0 ? adc (not available on f551x devices) general-purpose digital i/o p6.1/cb1/a1 78 2 c3 b2 i/o comparator_b input cb1 analog input a1 ? adc (not available on f551x devices) general-purpose digital i/o p6.2/cb2/a2 79 3 a1 b1 i/o comparator_b input cb2 analog input a2 ? adc (not available on f551x devices) general-purpose digital i/o p6.3/cb3/a3 80 4 c4 c2 i/o comparator_b input cb3 analog input a3 ? adc (not available on f551x devices) reserved n/a n/a n/a (6) reserved. connect to ground. qfn pad n/a pad n/a n/a qfn package pad. ti recommends connecting to v ss . (5) when this pin is configured as reset, the internal pullup resistor is enabled by default. (6) c6, d4, d5, d6, e3, e4, e5, e6, f3, f4, f5, f6, f7, f8, g3 are reserved and should be connected to ground. 18 terminal configuration and functions copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5 specifications 5.1 absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit voltage applied at v cc to v ss ? 0.3 4.1 v voltage applied to any pin (excluding vcore, vbus, v18) (2) ? 0.3 v cc + 0.3 v diode current at any device pin 2 ma maximum operating junction temperature, t j 95 c storage temperature, t stg (3) ? 55 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages referenced to v ss . vcore is for internal device use only. no external dc loading or voltage should be applied. (3) higher temperature may be applied during board soldering according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. 5.2 esd ratings value unit human-body model (hbm), per ansi/esda/jedec js-001 (1) 1000 v (esd) electrostatic discharge v charged-device model (cdm), per jedec specification jesd22-c101 (2) 250 (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. pins listed as 1000 v may actually have higher performance. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. pins listed as 250 v may actually have higher performance. 5.3 recommended operating conditions typical values are specified at v cc = 3.3 v and t a = 25 c (unless otherwise noted) min nom max unit pmmcorevx = 0 1.8 3.6 pmmcorevx = 0, 1 2.0 3.6 supply voltage during program execution and flash v cc v programming (av cc = dv cc1/2 = dv cc ) (1) (2) pmmcorevx = 0, 1, 2 2.2 3.6 pmmcorevx = 0, 1, 2, 3 2.4 3.6 pmmcorevx = 0 1.8 3.6 pmmcorevx = 0, 1 2.0 3.6 supply voltage during usb operation, usb pll disabled, usb_en = 1, upllen = 0 pmmcorevx = 0, 1, 2 2.2 3.6 v cc, usb v pmmcorevx = 0, 1, 2, 3 2.4 3.6 pmmcorevx = 2 2.2 3.6 supply voltage during usb operation, usb pll enabled (3) , usb_en = 1, upllen = 1 pmmcorevx = 2, 3 2.4 3.6 v ss supply voltage (av ss = dv ss1/2 = dv ss ) 0 v t a operating free-air temperature i version ? 40 85 c t j operating junction temperature i version ? 40 85 c c vcore recommended capacitor at vcore (4) 470 nf c dvcc / capacitor ratio of dvcc to vcore 10 ratio c vcore (1) ti recommends powering avcc and dvcc from the same source. a maximum difference of 0.3 v between avcc and dvcc can be tolerated during power up and operation. (2) the minimum supply voltage is defined by the supervisor svs levels when it is enabled. see the section 5.22 threshold parameters for the exact values and further details. (3) usb operation with usb pll enabled requires pmmcorevx 2 for proper operation. (4) a capacitor tolerance of 20% or better is required. copyright ? 2009 ? 2015, texas instruments incorporated specifications 19 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com recommended operating conditions (continued) typical values are specified at v cc = 3.3 v and t a = 25 c (unless otherwise noted) min nom max unit pmmcorevx = 0, 1.8 v v cc 3.6 v 0 8.0 (default condition) pmmcorevx = 1, 0 12.0 processor frequency (maximum mclk frequency) (5) 2.0 v v cc 3.6 v f system mhz (see figure 5-1 ) pmmcorevx = 2, 0 20.0 2.2 v v cc 3.6 v pmmcorevx = 3, 0 25.0 2.4 v v cc 3.6 v f system_usb minimum processor frequency for usb operation 1.5 mhz usb_wait wait state cycles during usb operation 16 cycles (5) modules may have a different maximum input clock specification. see the specification of the respective module in this data sheet. figure 5-1. maximum system frequency 20 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 2.0 1.8 8 0 12 20 25 system frequency - mhz supply voltage - v the numbers within the fields denote the supported pmmcorevx settings. 2.2 2.4 3.6 0, 1, 2, 3 0, 1, 2 0, 1 0 1, 2, 3 1, 2 1 2, 3 3 2
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.4 active mode supply current into v cc excluding external current over recommended operating free-air temperature (unless otherwise noted) (1) (2) (3) frequency (f dco = f mclk = f smclk ) execution parameter v cc pmmcorevx 1 mhz 8 mhz 12 mhz 20 mhz 25 mhz unit memory typ max typ max typ max typ max typ max 0 0.36 0.47 2.32 2.60 1 0.40 2.65 4.0 4.4 i am, flash flash 3.0 v ma 2 0.44 2.90 4.3 7.1 7.7 3 0.46 3.10 4.6 7.6 10.1 11.0 0 0.20 0.24 1.20 1.30 1 0.22 1.35 2.0 2.2 i am, ram ram 3.0 v ma 2 0.24 1.50 2.2 3.7 4.2 3 0.26 1.60 2.4 3.9 5.3 6.2 (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf. (3) characterized with program executing typical data processing. usb disabled (vusben = 0, sldoen = 0). f aclk = 32786 hz, f dco = f mclk = f smclk at specified frequency. xts = cpuoff = scg0 = scg1 = oscoff= smclkoff = 0. copyright ? 2009 ? 2015, texas instruments incorporated specifications 21 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.5 low-power mode supply currents (into v cc ) excluding external current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) ? 40 c 25 c 60 c 85 c parameter v cc pmmcorevx unit typ max typ max typ max typ max 2.2 v 0 73 77 85 80 85 97 i lpm0,1mhz low-power mode 0 (3) (4) a 3.0 v 3 79 83 92 88 95 105 2.2 v 0 6.5 6.5 12 10 11 17 i lpm2 low-power mode 2 (5) (4) a 3.0 v 3 7.0 7.0 13 11 12 18 0 1.60 1.90 2.6 5.6 2.2 v 1 1.65 2.00 2.7 5.9 2 1.75 2.15 2.9 6.1 low-power mode 3, i lpm3,xt1lf 0 1.8 2.1 2.9 2.8 5.8 8.3 a crystal mode (6) (4) 1 1.9 2.3 2.9 6.1 3.0 v 2 2.0 2.4 3.0 6.3 3 2.0 2.5 3.9 3.1 6.4 9.3 0 1.1 1.4 2.7 1.9 4.9 7.4 1 1.1 1.4 2.0 5.2 low-power mode 3, i lpm3,vlo 3.0 v a vlo mode (7) (4) 2 1.2 1.5 2.1 5.3 3 1.3 1.6 3.0 2.2 5.4 8.5 0 0.9 1.1 1.5 1.8 4.8 7.3 1 1.1 1.2 2.0 5.1 i lpm4 low-power mode 4 (8) (4) 3.0 v a 2 1.2 1.2 2.1 5.2 3 1.3 1.3 1.6 2.2 5.3 8.1 i lpm4.5 low-power mode 4.5 (9) 3.0 v 0.15 0.18 0.35 0.26 0.5 1.0 a (1) all inputs are tied to 0 v or to v cc . outputs do not source or sink any current. (2) the currents are characterized with a micro crystal ms1v-t1k crystal with a load capacitance of 12.5 pf. the internal and external load capacitance are chosen to closely match the required 12.5 pf. (3) current for watchdog timer clocked by smclk included. aclk = low frequency crystal operation (xts = 0, xt1drivex = 0). cpuoff = 1, scg0 = 0, scg1 = 0, oscoff = 0 (lpm0); f aclk = 32768 hz, f mclk = 0 mhz, f smclk = f dco = 1 mhz usb disabled (vusben = 0, sldoen = 0). (4) current for brownout, high-side supervisor (svs h ) normal mode included. low-side supervisor and monitor disabled (svs l , svm l ). high-side monitor disabled (svm h ). ram retention enabled. (5) current for watchdog timer and rtc clocked by aclk included. aclk = low frequency crystal operation (xts = 0, xt1drivex = 0). cpuoff = 1, scg0 = 0, scg1 = 1, oscoff = 0 (lpm2); f aclk = 32768 hz, f mclk = 0 mhz, f smclk = f dco = 0 mhz; dco setting = 1 mhz operation, dco bias generator enabled. usb disabled (vusben = 0, sldoen = 0) (6) current for watchdog timer and rtc clocked by aclk included. aclk = low frequency crystal operation (xts = 0, xt1drivex = 0). cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 0 (lpm3); f aclk = 32768 hz, f mclk = f smclk = f dco = 0 mhz usb disabled (vusben = 0, sldoen = 0) (7) current for watchdog timer and rtc clocked by aclk included. aclk = vlo. cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 0 (lpm3); f aclk = f vlo , f mclk = f smclk = f dco = 0 mhz usb disabled (vusben = 0, sldoen = 0) (8) cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 1 (lpm4); f dco = f aclk = f mclk = f smclk = 0 mhz usb disabled (vusben = 0, sldoen = 0) (9) internal regulator disabled. no data retention. cpuoff = 1, scg0 = 1, scg1 = 1, oscoff = 1, pmmregoff = 1 (lpm4.5); f dco = f aclk = f mclk = f smclk = 0 mhz 22 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.6 thermal characteristics parameter value unit lqfp (pn) 70 low-k board (jesd51-3) vqfn (rgc) 55 bga (zqe) 84 ja junction-to-ambient thermal resistance, still air c/w lqfp (pn) 45 high-k board (jesd51-7) vqfn (rgc) 25 bga (zqe) 46 lqfp (pn) 12 jc junction-to-case thermal resistance vqfn (rgc) 12 c/w bga (zqe) 30 lqfp (pn) 22 jb junction-to-board thermal resistance vqfn (rgc) 6 c/w bga (zqe) 20 copyright ? 2009 ? 2015, texas instruments incorporated specifications 23 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.7 schmitt-trigger inputs ? general-purpose i/o (1) (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3, rst /nmi) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 1.8 v 0.80 1.40 v it+ positive-going input threshold voltage v 3 v 1.50 2.10 1.8 v 0.45 1.00 v it ? negative-going input threshold voltage v 3 v 0.75 1.65 1.8 v 0.3 0.85 v hys input voltage hysteresis (v it+ ? v it ? ) v 3 v 0.4 1.0 for pullup: v in = v ss r pull pullup and pulldown resistor (2) 20 35 50 k for pulldown: v in = v cc c i input capacitance v in = v ss or v cc 5 pf (1) same parametrics apply to clock input pin when crystal bypass mode is used on xt1 (xin) or xt2 (xt2in). (2) also applies to rst pin when pullup or pulldown resistor is enabled. 5.8 inputs ? ports p1 and p2 (1) (p1.0 to p1.7, p2.0 to p2.7) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit t (int) external interrupt timing (2) external trigger pulse duration to set interrupt flag 2.2 v, 3 v 20 ns (1) some devices may contain additional ports with interrupts. see the block diagram and terminal function descriptions. (2) an external signal sets the interrupt flag every time the minimum interrupt pulse duration t (int) is met. it may be set by trigger signals shorter than t (int) . 5.9 leakage current ? general-purpose i/o (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3, rst /nmi) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit i lkg(px.x) high-impedance leakage current (1) (2) 1.8 v, 3 v ? 50 50 na (1) the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. (2) the leakage of the digital port pins is measured individually. the port pin is selected for input and the pullup or pulldown resistor is disabled. 5.10 outputs ? general-purpose i/o (full drive strength) (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit i (ohmax) = ? 3 ma (1) v cc ? 0.25 v cc 1.8 v i (ohmax) = ? 10 ma (2) v cc ? 0.60 v cc v oh high-level output voltage v i (ohmax) = ? 5 ma (1) v cc ? 0.25 v cc 3 v i (ohmax) = ? 15 ma (2) v cc ? 0.60 v cc i (olmax) = 3 ma (1) v ss v ss + 0.25 1.8 v i (olmax) = 10 ma (2) v ss v ss + 0.60 v ol low-level output voltage v i (olmax) = 5 ma (1) v ss v ss + 0.25 3 v i (olmax) = 15 ma (2) v ss v ss + 0.60 (1) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 48 ma to hold the maximum voltage drop specified. (2) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined should not exceed 100 ma to hold the maximum voltage drop specified. 24 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.11 outputs ? general-purpose i/o (reduced drive strength) (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min max unit i (ohmax) = ? 1 ma (2) v cc ? 0.25 v cc 1.8 v i (ohmax) = ? 3 ma (3) v cc ? 0.60 v cc v oh high-level output voltage v i (ohmax) = ? 2 ma (2) v cc ? 0.25 v cc 3.0 v i (ohmax) = ? 6 ma (3) v cc ? 0.60 v cc i (olmax) = 1 ma (2) v ss v ss + 0.25 1.8 v i (olmax) = 3 ma (3) v ss v ss + 0.60 v ol low-level output voltage v i (olmax) = 2 ma (2) v ss v ss + 0.25 3.0 v i (olmax) = 6 ma (3) v ss v ss + 0.60 (1) selecting reduced drive strength may reduce emi. (2) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. (3) the maximum total current, i (ohmax) and i (olmax) , for all outputs combined, should not exceed 100 ma to hold the maximum voltage drop specified. 5.12 output frequency ? general-purpose i/o (p1.0 to p1.7, p2.0 to p2.7, p3.0 to p3.7, p4.0 to p4.7) (p5.0 to p5.7, p6.0 to p6.7, p7.0 to p7.7, p8.0 to p8.2, pj.0 to pj.3) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v cc = 1.8 v, 16 pmmcorevx = 0 port output frequency f px.y see (1) (2) mhz (with load) v cc = 3 v, 25 pmmcorevx = 3 v cc = 1.8 v, aclk, 16 pmmcorevx = 0 smclk, f port_clk clock output frequency mhz mclk, v cc = 3 v, 25 c l = 20 pf (2) pmmcorevx = 3 (1) a resistive divider with 2 r1 between v cc and v ss is used as load. the output is connected to the center tap of the divider. for full drive strength, r1 = 550 . for reduced drive strength, r1 = 1.6 k . c l = 20 pf is connected to the output to v ss . (2) the output voltage reaches at least 10% and 90% v cc at the specified toggle frequency. copyright ? 2009 ? 2015, texas instruments incorporated specifications 25 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.13 typical characteristics ? outputs, reduced drive strength (pxds.y = 0) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 5-3. typical low-level output current vs low-level figure 5-2. typical low-level output current vs low-level output voltage output voltage figure 5-5. typical high-level output current vs high-level figure 5-4. typical high-level output current vs high-level output voltage output voltage 26 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t = 25c a t = 85c a v = 3.0 v px.y cc v ? high-level output voltage ? v oh i ? typical high-level output current ? ma oh -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 0.0 0.5 1.0 1.5 2.0 t = 25c a t = 85c a v = 1.8 v px.y cc v ? high-level output voltage ? v oh i ? typical high-level output current ? ma oh 0.0 5.0 10.0 15.0 20.0 25.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t = 25c a t = 85c a v = 3.0 v px.y cc v ? low-level output voltage ? v ol i ? typical low-level output current ? ma ol 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 0.0 0.5 1.0 1.5 2.0 t = 25c a t = 85c a v = 1.8 v px.y cc v ? low-level output voltage ? v ol i ? typical low-level output current ? ma ol
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.14 typical characteristics ? outputs, full drive strength (pxds.y = 1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) figure 5-7. typical low-level output current vs low-level figure 5-6. typical low-level output current vs low-level output voltage output voltage figure 5-8. typical high-level output current vs high-level figure 5-9. typical high-level output current vs high-level output voltage output voltage copyright ? 2009 ? 2015, texas instruments incorporated specifications 27 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 -20 -16 -12 -8 -4 0 0.0 0.5 1.0 1.5 2.0 t = 25c a t = 85c a v = 1.8 v px.y cc v ? high-level output voltage ? v oh i ? typical high-level output current ? ma oh -60.0 -55.0 -50.0 -45.0 -40.0 -35.0 -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t = 25c a t = 85c a v = 3.0 v px.y cc v ? high-level output voltage ? v oh i ? typical high-level output current ? ma oh 0.0 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 60.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 t = 25c a t = 85c a v = 3.0 v px.y cc v ? low-level output voltage ? v ol i ? typical low-level output current ? ma ol 0 4 8 12 16 20 24 0.0 0.5 1.0 1.5 2.0 t = 25c a t = 85c a v = 1.8 v px.y cc v ? low-level output voltage ? v ol i ? typical low-level output current ? ma ol
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.15 crystal oscillator, xt1, low-frequency mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f osc = 32768 hz, xts = 0, xt1bypass = 0, 0.075 xt1drivex = 1, t a = 25 c differential xt1 oscillator crystal current consumption f osc = 32768 hz, xts = 0, xt1bypass = 0, i dvcc.lf 3.0 v 0.170 a from lowest drive setting, lf xt1drivex = 2, t a = 25 c mode f osc = 32768 hz, xts = 0, xt1bypass = 0, 0.290 xt1drivex = 3, t a = 25 c xt1 oscillator crystal f xt1,lf0 xts = 0, xt1bypass = 0 32768 hz frequency, lf mode xt1 oscillator logic-level f xt1,lf,sw square-wave input frequency, xts = 0, xt1bypass = 1 (2) (3) 10 32.768 50 khz lf mode xts = 0, xt1bypass = 0, xt1drivex = 0, 210 f xt1,lf = 32768 hz, c l,eff = 6 pf oscillation allowance for oa lf k lf crystals (4) xts = 0, xt1bypass = 0, xt1drivex = 1, 300 f xt1,lf = 32768 hz, c l,eff = 12 pf xts = 0, xcapx = 0 (6) 1 xts = 0, xcapx = 1 5.5 integrated effective load c l,eff pf capacitance, lf mode (5) xts = 0, xcapx = 2 8.5 xts = 0, xcapx = 3 12.0 xts = 0, measured at aclk, duty cycle, lf mode 30% 70% f xt1,lf = 32768 hz oscillator fault frequency, f fault,lf xts = 0 (8) 10 10000 hz lf mode (7) f osc = 32768 hz, xts = 0, xt1bypass = 0, 1000 xt1drivex = 0, t a = 25 c, c l,eff = 6 pf t start,lf start-up time, lf mode 3.0 v ms f osc = 32768 hz, xts = 0, xt1bypass = 0, 500 xt1drivex = 3, t a = 25 c, c l,eff = 12 pf (1) to improve emi on the xt1 oscillator, the following guidelines should be observed. ? keep the trace between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins xin and xout. ? avoid running pcb traces underneath or adjacent to the xin and xout pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator xin and xout pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (2) when xt1bypass is set, xt1 circuits are automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this data sheet. (3) maximum frequency of operation of the entire device cannot be exceeded. (4) oscillation allowance is based on a safety factor of 5 for recommended crystals. the oscillation allowance is a function of the xt1drivex settings and the effective load. in general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application: ? for xt1drivex = 0, c l,eff 6 pf. ? for xt1drivex = 1, 6 pf c l,eff 9 pf. ? for xt1drivex = 2, 6 pf c l,eff 10 pf. ? for xt1drivex = 3, c l,eff 6 pf. (5) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, ti recommends verifying the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the used crystal. (6) requires external capacitors at both terminals. values are specified by crystal manufacturers. (7) frequencies below the min specification set the fault flag. frequencies above the max specification do not set the fault flag. frequencies between the min and max specifications might set the flag. (8) measured with logic-level input frequency but also applies to operation with crystals. 28 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.16 crystal oscillator, xt2 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) parameter test conditions v cc min typ max unit f osc = 4 mhz, xt2off = 0, xt2bypass = 0, 200 xt2drivex = 0, t a = 25 c f osc = 12 mhz, xt2off = 0, xt2bypass = 0, 260 xt2drivex = 1, t a = 25 c xt2 oscillator crystal i dvcc.xt2 3.0 v a current consumption f osc = 20 mhz, xt2off = 0, xt2bypass = 0, 325 xt2drivex = 2, t a = 25 c f osc = 32 mhz, xt2off = 0, xt2bypass = 0, 450 xt2drivex = 3, t a = 25 c xt2 oscillator crystal f xt2,hf0 xt2drivex = 0, xt2bypass = 0 (3) 4 8 mhz frequency, mode 0 xt2 oscillator crystal f xt2,hf1 xt2drivex = 1, xt2bypass = 0 (3) 8 16 mhz frequency, mode 1 xt2 oscillator crystal f xt2,hf2 xt2drivex = 2, xt2bypass = 0 (3) 16 24 mhz frequency, mode 2 xt2 oscillator crystal f xt2,hf3 xt2drivex = 3, xt2bypass = 0 (3) 24 32 mhz frequency, mode 3 xt2 oscillator logic-level f xt2,hf,sw square-wave input xt2bypass = 1 (4) (3) 0.7 32 mhz frequency, bypass mode xt2drivex = 0, xt2bypass = 0, 450 f xt2,hf0 = 6 mhz, c l,eff = 15 pf xt2drivex = 1, xt2bypass = 0, 320 f xt2,hf1 = 12 mhz, c l,eff = 15 pf oscillation allowance for oa hf hf crystals (5) xt2drivex = 2, xt2bypass = 0, 200 f xt2,hf2 = 20 mhz, c l,eff = 15 pf xt2drivex = 3, xt2bypass = 0, 200 f xt2,hf3 = 32 mhz, c l,eff = 15 pf f osc = 6 mhz, xt2bypass = 0, xt2drivex = 0, 0.5 t a = 25 c, c l,eff = 15 pf t start,hf start-up time 3.0 v ms f osc = 20 mhz, xt2bypass = 0, xt2drivex = 2, 0.3 t a = 25 c, c l,eff = 15 pf integrated effective load c l,eff capacitance, hf 1 pf mode (6) (1) duty cycle measured at aclk, f xt2,hf2 = 20 mhz 40% 50% 60% oscillator fault f fault,hf xt2bypass = 1 (8) 30 300 khz frequency (7) (1) requires external capacitors at both terminals. values are specified by crystal manufacturers. in general, an effective load capacitance of up to 18 pf can be supported. (2) to improve emi on the xt2 oscillator the following guidelines should be observed. ? keep the traces between the device and the crystal as short as possible. ? design a good ground plane around the oscillator pins. ? prevent crosstalk from other clock or data lines into oscillator pins xt2in and xt2out. ? avoid running pcb traces underneath or adjacent to the xt2in and xt2out pins. ? use assembly materials and processes that avoid any parasitic load on the oscillator xt2in and xt2out pins. ? if conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins. (3) this represents the maximum frequency that can be input to the device externally. maximum frequency achievable on the device operation is based on the frequencies present on aclk, mclk, and smclk cannot be exceed for a given range of operation. (4) when xt2bypass is set, the xt2 circuit is automatically powered down. input signal is a digital square wave with parametrics defined in the schmitt-trigger inputs section of this data sheet. (5) oscillation allowance is based on a safety factor of 5 for recommended crystals. (6) includes parasitic bond and package capacitance (approximately 2 pf per pin). because the pcb adds additional capacitance, ti recommends verifying the correct load by measuring the aclk frequency. for a correct setup, the effective load capacitance should always match the specification of the used crystal. (7) frequencies below the min specification set the fault flag. frequencies above the max specification do not set the fault flag. frequencies between the min and max specifications might set the flag. (8) measured with logic-level input frequency but also applies to operation with crystals. copyright ? 2009 ? 2015, texas instruments incorporated specifications 29 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.17 internal very-low-power low-frequency oscillator (vlo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit f vlo vlo frequency measured at aclk 1.8 v to 3.6 v 6 9.4 14 khz df vlo /d t vlo frequency temperature drift measured at aclk (1) 1.8 v to 3.6 v 0.5 %/ c df vlo /dv cc vlo frequency supply voltage drift measured at aclk (2) 1.8 v to 3.6 v 4 %/v duty cycle measured at aclk 1.8 v to 3.6 v 40% 50% 60% (1) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(1.8 v to 3.6 v) ? min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v ? 1.8 v) 5.18 internal reference, low-frequency oscillator (refo) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i refo refo oscillator current consumption t a = 25 c 1.8 v to 3.6 v 3 a refo frequency calibrated measured at aclk 1.8 v to 3.6 v 32768 hz f refo full temperature range 1.8 v to 3.6 v ? 3.5% 3.5% refo absolute tolerance calibrated t a = 25 c 3 v ? 1.5% 1.5% df refo /d t refo frequency temperature drift measured at aclk (1) 1.8 v to 3.6 v 0.01 %/ c df refo /dv cc refo frequency supply voltage drift measured at aclk (2) 1.8 v to 3.6 v 1.0 %/v duty cycle measured at aclk 1.8 v to 3.6 v 40% 50% 60% t start refo start-up time 40%/60% duty cycle 1.8 v to 3.6 v 25 s (1) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (2) calculated using the box method: (max(1.8 v to 3.6 v) ? min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v ? 1.8 v) 30 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.19 dco frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit f dco(0,0) dco frequency (0, 0) (1) dcorselx = 0, dcox = 0, modx = 0 0.07 0.20 mhz f dco(0,31) dco frequency (0, 31) (1) dcorselx = 0, dcox = 31, modx = 0 0.70 1.70 mhz f dco(1,0) dco frequency (1, 0) (1) dcorselx = 1, dcox = 0, modx = 0 0.15 0.36 mhz f dco(1,31) dco frequency (1, 31) (1) dcorselx = 1, dcox = 31, modx = 0 1.47 3.45 mhz f dco(2,0) dco frequency (2, 0) (1) dcorselx = 2, dcox = 0, modx = 0 0.32 0.75 mhz f dco(2,31) dco frequency (2, 31) (1) dcorselx = 2, dcox = 31, modx = 0 3.17 7.38 mhz f dco(3,0) dco frequency (3, 0) (1) dcorselx = 3, dcox = 0, modx = 0 0.64 1.51 mhz f dco(3,31) dco frequency (3, 31) (1) dcorselx = 3, dcox = 31, modx = 0 6.07 14.0 mhz f dco(4,0) dco frequency (4, 0) (1) dcorselx = 4, dcox = 0, modx = 0 1.3 3.2 mhz f dco(4,31) dco frequency (4, 31) (1) dcorselx = 4, dcox = 31, modx = 0 12.3 28.2 mhz f dco(5,0) dco frequency (5, 0) (1) dcorselx = 5, dcox = 0, modx = 0 2.5 6.0 mhz f dco(5,31) dco frequency (5, 31) (1) dcorselx = 5, dcox = 31, modx = 0 23.7 54.1 mhz f dco(6,0) dco frequency (6, 0) (1) dcorselx = 6, dcox = 0, modx = 0 4.6 10.7 mhz f dco(6,31) dco frequency (6, 31) (1) dcorselx = 6, dcox = 31, modx = 0 39.0 88.0 mhz f dco(7,0) dco frequency (7, 0) (1) dcorselx = 7, dcox = 0, modx = 0 8.5 19.6 mhz f dco(7,31) dco frequency (7, 31) (1) dcorselx = 7, dcox = 31, modx = 0 60 135 mhz frequency step between range s dcorsel s rsel = f dco(dcorsel+1,dco) /f dco(dcorsel,dco) 1.2 2.3 ratio dcorsel and dcorsel + 1 frequency step between tap s dco s dco = f dco(dcorsel,dco+1) /f dco(dcorsel,dco) 1.02 1.12 ratio dco and dco + 1 duty cycle measured at smclk 40% 50% 60% dco frequency temperature df dco /dt f dco = 1 mhz 0.1 %/ c drift (2) df dco /dv cc dco frequency voltage drift (3) f dco = 1 mhz 1.9 %/v (1) when selecting the proper dco frequency range (dcorselx), the target dco frequency, f dco , should be set to reside within the range of f dco(n, 0),max f dco f dco(n, 31),min , where f dco(n, 0),max represents the maximum frequency specified for the dco frequency, range n, tap 0 (dcox = 0) and f dco(n,31),min represents the minimum frequency specified for the dco frequency, range n, tap 31 (dcox = 31). this ensures that the target dco frequency resides within the range selected. it should also be noted that if the actual f dco frequency for the selected range causes the fll or the application to select tap 0 or 31, the dco fault flag is set to report that the selected range is at its minimum or maximum tap setting. (2) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c) / (85 c ? ( ? 40 c)) (3) calculated using the box method: (max(1.8 v to 3.6 v) ? min(1.8 v to 3.6 v)) / min(1.8 v to 3.6 v) / (3.6 v ? 1.8 v) figure 5-10. typical dco frequency copyright ? 2009 ? 2015, texas instruments incorporated specifications 31 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 0 1 2 3 4 5 6 7 typical dco frequency, v = 3.0 v, t = 25c cc a dcorsel 100 10 1 0.1 f ? mhz dco dcox = 31 dcox = 0
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.20 pmm, brown-out reset (bor) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit v(dv cc _bor_it ? ) bor h on voltage, dv cc falling level | ddv cc /d t | < 3 v/s 1.45 v v(dv cc _bor_it+) bor h off voltage, dv cc rising level | ddv cc /d t | < 3 v/s 0.80 1.30 1.50 v v(dv cc _bor_hys) bor h hysteresis 60 250 mv pulse duration required at rst/nmi pin t reset 2 s to accept a reset 5.21 pmm, core voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit v core3 (am) core voltage, active mode, pmmcorev = 3 2.4 v dv cc 3.6 v 1.90 v v core2 (am) core voltage, active mode, pmmcorev = 2 2.2 v dv cc 3.6 v 1.80 v v core1 (am) core voltage, active mode, pmmcorev = 1 2.0 v dv cc 3.6 v 1.60 v v core0 (am) core voltage, active mode, pmmcorev = 0 1.8 v dv cc 3.6 v 1.40 v core voltage, low-current mode, v core3 (lpm) 2.4 v dv cc 3.6 v 1.94 v pmmcorev = 3 core voltage, low-current mode, v core2 (lpm) 2.2 v dv cc 3.6 v 1.84 v pmmcorev = 2 core voltage, low-current mode, v core1 (lpm) 2.0 v dv cc 3.6 v 1.64 v pmmcorev = 1 core voltage, low-current mode, v core0 (lpm) 1.8 v dv cc 3.6 v 1.44 v pmmcorev = 0 5.22 pmm, svs high side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit svshe = 0, dv cc = 3.6 v 0 na i (svsh) svs current consumption svshe = 1, dv cc = 3.6 v, svshfp = 0 200 na svshe = 1, dv cc = 3.6 v, svshfp = 1 1.5 a svshe = 1, svshrvl = 0 1.57 1.68 1.78 svshe = 1, svshrvl = 1 1.79 1.88 1.98 v (svsh_it ? ) svs h on voltage level (1) v svshe = 1, svshrvl = 2 1.98 2.08 2.21 svshe = 1, svshrvl = 3 2.10 2.18 2.31 svshe = 1, svsmhrrl = 0 1.62 1.74 1.85 svshe = 1, svsmhrrl = 1 1.88 1.94 2.07 svshe = 1, svsmhrrl = 2 2.07 2.14 2.28 svshe = 1, svsmhrrl = 3 2.20 2.30 2.42 v (svsh_it+) svs h off voltage level (1) v svshe = 1, svsmhrrl = 4 2.32 2.40 2.55 svshe = 1, svsmhrrl = 5 2.52 2.70 2.88 svshe = 1, svsmhrrl = 6 2.90 3.10 3.23 svshe = 1, svsmhrrl = 7 2.90 3.10 3.23 svshe = 1, dv dvcc /dt = 10 mv/ s, svshfp = 1 2.5 t pd(svsh) svs h propagation delay s svshe = 1, dv dvcc /dt = 1 mv/ s, svshfp = 0 20 svshe = 0 1, svshfp = 1 12.5 t (svsh) svs h on or off delay time s svshe = 0 1, svshfp = 0 100 dv dvcc /dt dvcc rise time 0 1000 v/s (1) the svs h settings available depend on the vcore (pmmcorevx) setting. see the power management module and supply voltage supervisor chapter in the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ) on recommended settings and use. 32 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.23 pmm, svm high side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit svmhe = 0, dv cc = 3.6 v 0 na i (svmh) svm h current consumption svmhe= 1, dv cc = 3.6 v, svmhfp = 0 200 na svmhe = 1, dv cc = 3.6 v, svmhfp = 1 1.5 a svmhe = 1, svsmhrrl = 0 1.62 1.74 1.85 svmhe = 1, svsmhrrl = 1 1.88 1.94 2.07 svmhe = 1, svsmhrrl = 2 2.07 2.14 2.28 svmhe = 1, svsmhrrl = 3 2.20 2.30 2.42 v (svmh) svm h on or off voltage level (1) svmhe = 1, svsmhrrl = 4 2.32 2.40 2.55 v svmhe = 1, svsmhrrl = 5 2.52 2.70 2.88 svmhe = 1, svsmhrrl = 6 2.90 3.10 3.23 svmhe = 1, svsmhrrl = 7 2.90 3.10 3.23 svmhe = 1, svmhovpe = 1 3.75 svmhe = 1, dv dvcc /dt = 10 mv/ s, svmhfp = 1 2.5 t pd(svmh) svm h propagation delay s svmhe = 1, dv dvcc /dt = 1 mv/ s, svmhfp = 0 20 svmhe = 0 1, svmhfp = 1 12.5 t (svmh) svm h on or off delay time s svmhe = 0 1, svmhfp = 0 100 (1) the svm h settings available depend on the vcore (pmmcorevx) setting. see the power management module and supply voltage supervisor chapter in the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ) on recommended settings and use. 5.24 pmm, svs low side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit svsle = 0, pmmcorev = 2 0 na i (svsl) svs l current consumption svsle = 1, pmmcorev = 2, svslfp = 0 200 na svsle = 1, pmmcorev = 2, svslfp = 1 1.5 a svsle = 1, dv core /dt = 10 mv/ s, svslfp = 1 2.5 t pd(svsl) svs l propagation delay s svsle = 1, dv core /dt = 1 mv/ s, svslfp = 0 20 svsle = 0 1, dv core /dt = 10 mv/ s, svslfp = 1 12.5 t (svsl) svs l on or off delay time s svsle = 0 1, dv core /dt = 1 mv/ s, svslfp = 0 100 5.25 pmm, svm low side over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit svmle = 0, pmmcorev = 2 0 na i (svml) svm l current consumption svmle= 1, pmmcorev = 2, svmlfp = 0 200 na svmle= 1, pmmcorev = 2, svmlfp = 1 1.5 a svmle = 1, dv core /dt = 10 mv/ s, svmlfp = 1 2.5 t pd(svml) svm l propagation delay s svmle = 1, dv core /dt = 1 mv/ s, svmlfp = 0 20 svmle = 0 1, dv core /dt = 10 mv/ s, svmlfp = 1 12.5 t (svml) svm l on or off delay time s svmle = 0 1, dv core /dt = 1 mv/ s, svmlfp = 0 100 copyright ? 2009 ? 2015, texas instruments incorporated specifications 33 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.26 wake-up times from low-power modes and reset over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min typ max unit f mclk 4.0 mhz 3.5 7.5 wake-up time from lpm2, pmmcorev = svsmlrrl = n t wake-up-fast lpm3, or lpm4 to active (where n = 0, 1, 2, or 3), s 1.0 mhz < f mclk 4.5 9 mode (1) svslfp = 1 < 4.0 mhz wake-up time from lpm2, pmmcorev = svsmlrrl = n t wake-up-slow lpm3 or lpm4 to active 150 165 s (where n = 0, 1, 2, or 3), svslfp = 0 mode (2) wake-up time from lpm4.5 to t wake-up-lpm5 2 3 ms active mode (3) wake-up time from rst or t wake-up-reset 2 3 ms bor event to active mode (3) (1) this value represents the time from the wake-up event to the first active edge of mclk. the wake-up time depends on the performance mode of the low-side supervisor (svs l ) and low-side monitor (svm l ). fastest wake-up times are possible with svs l and svm l in full- performance mode or disabled when operating in am, lpm0, and lpm1. various options are available for svs l and svm l while operating in lpm2, lpm3, and lpm4. see the power management module and supply voltage supervisor chapter in the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ). (2) this value represents the time from the wake-up event to the first active edge of mclk. the wake-up time depends on the performance mode of the low-side supervisor (svs l ) and low-side monitor (svm l ). in this case, the svs l and svm l are in normal mode (low current) mode when operating in am, lpm0, and lpm1. various options are available for svs l and svm l while operating in lpm2, lpm3, and lpm4. see the power management module and supply voltage supervisor chapter in the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ). (3) this value represents the time from the wake-up event to the reset vector execution. 5.27 timer_a over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit internal: smclk, aclk, f ta timer_a input clock frequency external: taclk, 1.8 v, 3 v 25 mhz duty cycle = 50% 10% all capture inputs, minimum pulse t ta,cap timer_a capture timing 1.8 v, 3 v 20 ns duration required for capture 5.28 timer_b over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit internal: smclk, aclk, f tb timer_b input clock frequency external: tbclk, 1.8 v, 3 v 25 mhz duty cycle = 50% 10% all capture inputs, minimum pulse t tb,cap timer_b capture timing 1.8 v, 3 v 20 ns duration required for capture 34 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.29 usci (uart mode) clock frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter conditions v cc min max unit internal: smclk, aclk, f usci usci input clock frequency external: uclk, f system mhz duty cycle = 50% 10% bitclk clock frequency f bitclk 1 mhz (equals baud rate in mbaud) 5.30 usci (uart mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min max unit 2.2 v 50 600 t t uart receive deglitch time (1) ns 3 v 50 600 (1) pulses on the uart receive input (ucxrx) shorter than the uart receive deglitch time are suppressed. to ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time. 5.31 usci (spi master mode) clock frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter conditions v cc min max unit internal: smclk, aclk, f usci usci input clock frequency f system mhz duty cycle = 50% 10% 5.32 usci (spi master mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see figure 5-11 and figure 5-12 ) parameter test conditions v cc min max unit smclk, aclk, f usci usci input clock frequency f system mhz duty cycle = 50% 10% 1.8 v 55 pmmcorev = 0 3.0 v 38 t su,mi somi input data setup time ns 2.4 v 30 pmmcorev = 3 3.0 v 25 1.8 v 0 pmmcorev = 0 3.0 v 0 t hd,mi somi input data hold time ns 2.4 v 0 pmmcorev = 3 3.0 v 0 1.8 v 20 uclk edge to simo valid, c l = 20 pf, pmmcorev = 0 3.0 v 18 t valid,mo simo output data valid time (2) ns 2.4 v 16 uclk edge to simo valid, c l = 20 pf, pmmcorev = 3 3.0 v 15 1.8 v ? 10 c l = 20 pf, pmmcorev = 0 3.0 v ? 8 t hd,mo simo output data hold time (3) ns 2.4 v ? 10 c l = 20 pf, pmmcorev = 3 3.0 v ? 8 (1) f ucxclk = 1/2t lo/hi with t lo/hi max(t valid,mo(usci) + t su,si(slave) , t su,mi(usci) + t valid,so(slave) ). for the slave parameters t su,si(slave) and t valid,so(slave) , see the spi parameters of the attached slave. (2) specifies the time to drive the next valid data to the simo output after the output changing uclk clock edge. see the timing diagrams in figure 5-11 and figure 5-12 . (3) specifies how long data on the simo output is valid after the output changing uclk clock edge. negative values indicate that the data on the simo output can become invalid before the output changing clock edge observed on uclk. see the timing diagrams in figure 5- 11 and figure 5-12 . copyright ? 2009 ? 2015, texas instruments incorporated specifications 35 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 5-11. spi master mode, ckph = 0 figure 5-12. spi master mode, ckph = 1 36 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 t su,mi t hd,mi uclk somi simo t valid,mo ckpl = 0 ckpl = 1 1/f ucxclk t hd,mo t lo/hi t lo/hi t su,mi t hd,mi uclk somi simo t valid,mo t hd,mo ckpl = 0 ckpl = 1 t lo/hi t lo/hi 1/f ucxclk
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.33 usci (spi slave mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (see figure 5-13 and figure 5-14 ) parameter test conditions v cc min typ max unit 1.8 v 11 pmmcorev = 0 3.0 v 8 t ste,lead ste lead time, ste low to clock ns 2.4 v 7 pmmcorev = 3 3.0 v 6 1.8 v 3 pmmcorev = 0 3.0 v 3 t ste,lag ste lag time, last clock to ste high ns 2.4 v 3 pmmcorev = 3 3.0 v 3 1.8 v 66 pmmcorev = 0 3.0 v 50 ste access time, ste low to somi data t ste,acc ns out 2.4 v 36 pmmcorev = 3 3.0 v 30 1.8 v 30 pmmcorev = 0 3.0 v 23 ste disable time, ste high to somi high t ste,dis ns impedance 2.4 v 16 pmmcorev = 3 3.0 v 13 1.8 v 5 pmmcorev = 0 3.0 v 5 t su,si simo input data setup time ns 2.4 v 2 pmmcorev = 3 3.0 v 2 1.8 v 5 pmmcorev = 0 3.0 v 5 t hd,si simo input data hold time ns 2.4 v 5 pmmcorev = 3 3.0 v 5 1.8 v 76 uclk edge to somi valid, c l = 20 pf, pmmcorev = 0 3.0 v 60 t valid,so somi output data valid time (2) ns 2.4 v 44 uclk edge to somi valid, c l = 20 pf, pmmcorev = 3 3.0 v 40 1.8 v 18 c l = 20 pf, pmmcorev = 0 3.0 v 12 t hd,so somi output data hold time (3) ns 2.4 v 10 c l = 20 pf, pmmcorev = 3 3.0 v 8 (1) f ucxclk = 1/2t lo/hi with t lo/hi max(t valid,mo(master) + t su,si(usci) , t su,mi(master) + t valid,so(usci) ). for the master parameters t su,mi(master) and t valid,mo(master) , see the spi parameters of the attached slave. (2) specifies the time to drive the next valid data to the somi output after the output changing uclk clock edge. see the timing diagrams in figure 5-13 and figure 5-14 . (3) specifies how long data on the somi output is valid after the output changing uclk clock edge. see the timing diagrams in figure 5-13 and figure 5-14 . copyright ? 2009 ? 2015, texas instruments incorporated specifications 37 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 5-13. spi slave mode, ckph = 0 figure 5-14. spi slave mode, ckph = 1 38 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 ste uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t ste,lead 1/f ucxclk t ste,lag t ste,dis t ste,acc t hd,mo t lo/hi t lo/hi ste uclk ckpl = 0 ckpl = 1 somi simo t su,si t hd,si t valid,so t ste,lead 1/f ucxclk t lo/hi t lo/hi t ste,lag t ste,dis t ste,acc t hd,so
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.34 usci (i 2 c mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 5-15 ) parameter test conditions v cc min max unit internal: smclk, aclk f usci usci input clock frequency external: uclk f system mhz duty cycle = 50% 10% f scl scl clock frequency 2.2 v, 3 v 0 400 khz f scl 100 khz 4.0 t hd,sta hold time (repeated) start 2.2 v, 3 v s f scl > 100 khz 0.6 f scl 100 khz 4.7 t su,sta setup time for a repeated start 2.2 v, 3 v s f scl > 100 khz 0.6 t hd,dat data hold time 2.2 v, 3 v 0 ns t su,dat data setup time 2.2 v, 3 v 250 ns f scl 100 khz 4.0 t su,sto setup time for stop 2.2 v, 3 v s f scl > 100 khz 0.6 2.2 v 50 600 pulse duration of spikes suppressed by input t sp ns filter 3 v 50 600 figure 5-15. i 2 c mode timing copyright ? 2009 ? 2015, texas instruments incorporated specifications 39 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 sda scl t hd,dat t su,dat t hd,sta t high t low t buf t hd,sta t su,sta t sp t su,sto
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.35 12-bit adc, power supply and input range conditions over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit avcc and dvcc are connected together, av cc analog supply voltage avss and dvss are connected together, 2.2 3.6 v v (avss) = v (dvss) = 0 v v (ax) analog input voltage range (2) all adc12 analog input pins ax 0 av cc v 2.2 v 125 155 operating supply current into i adc12_a f adc12clk = 5.0 mhz (4) a avcc terminal (3) 3 v 150 220 only one terminal ax can be selected at one c i input capacitance 2.2 v 20 25 pf time r i input mux on resistance 0 v v ax avcc 10 200 1900 (1) the leakage current is specified by the digital i/o input leakage. (2) the analog input voltage range must be within the selected reference voltage range v r+ to v r ? for valid conversion results. if the reference voltage is supplied by an external source or if the internal reference voltage is used and refout = 1, then decoupling capacitors are required. see section 5.40 and section 5.41 . (3) the internal reference supply current is not included in current consumption parameter i adc12_a . (4) adc12on = 1, refon = 0, sht0 = 0, sht1 = 0, adc12div = 0 5.36 12-bit adc, timing parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit for specified performance of adc12 linearity parameters using an external reference voltage or 0.45 4.8 5.0 avcc as reference (1) f adc12clk adc conversion clock for specified performance of adc12 linearity 2.2 v, 3 v mhz 0.45 2.4 4.0 parameters using the internal reference (2) for specified performance of adc12 linearity 0.45 2.4 2.7 parameters using the internal reference (3) internal adc12 f adc12osc adc12div = 0, f adc12clk = f adc12osc 2.2 v, 3 v 4.2 4.8 5.4 mhz oscillator (4) refon = 0, internal oscillator, 2.2 v, 3 v 2.4 3.1 adc12osc used for adc conversion clock t convert conversion time s external f adc12clk from aclk, mclk, or smclk, (5) adc12ssel 0 r s = 400 , r i = 1000 , c i = 20 pf, t sample sampling time 2.2 v, 3 v 1000 ns t = [r s + r i ] c i (6) (1) refout = 0, external reference voltage: sref2 = 0, sref1 = 1, sref0 = 0. avcc as reference voltage: sref2 = 0, sref1 = 0, sref0 = 0. the specified performance of the adc12 linearity is ensured when using the adc12osc. for other clock sources, the specified performance of the adc12 linearity is ensured with f adc12clk maximum of 5.0 mhz. (2) sref2 = 0, sref1 = 1, sref0 = 0, adc12sr = 0, refout = 1 (3) sref2 = 0, sref1 = 1, sref0 = 0, adc12sr = 0, refout = 0. the specified performance of the adc12 linearity is ensured when using the adc12osc divided by 2. (4) the adc12osc is sourced directly from modosc inside the ucs. (5) 13 adc12div 1/f adc12clk (6) approximately 10 tau (t) are needed to get an error of less than 0.5 lsb: t sample = ln(2 n+1 ) x (r s + r i ) c i + 800 ns, where n = adc resolution = 12, r s = external source resistance 40 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.37 12-bit adc, linearity parameters using an external reference voltage or avcc as reference voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 1.4 v dvref 1.6 v (2) 2.0 e i integral linearity error (1) 2.2 v, 3 v lsb 1.6 v < dvref (2) 1.7 e d differential linearity error (1) (2) 2.2 v, 3 v 1.0 lsb dvref 2.2 v (2) 2.2 v, 3 v 1.0 2.0 e o offset error (3) lsb dvref > 2.2 v (2) 2.2 v, 3 v 1.0 2.0 e g gain error (3) (2) 2.2 v, 3 v 1.0 2.0 lsb dvref 2.2 v (2) 2.2 v, 3 v 1.4 3.5 e t total unadjusted error lsb dvref > 2.2 v (2) 2.2 v, 3 v 1.4 3.5 (1) parameters are derived using the histogram method. (2) the external reference voltage is selected by: sref2 = 0 or 1, sref1 = 1, sref0 = 0. dvref = v r+ ? v r- , v r+ < avcc, v r- > avss. unless otherwise mentioned, dvref > 1.5 v. impedance of the external reference voltage r < 100 , and two decoupling capacitors, 10 f and 100 nf, should be connected to vref+ and vref- to decouple the dynamic current. also see the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ). (3) parameters are derived using a best fit curve. 5.38 12-bit adc, linearity parameters using the internal reference voltage over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions (1) v cc min typ max unit adc12sr = 0, refout = 1 f adc12clk = 4.0 mhz 1.7 integral linearity e i 2.2 v, 3 v lsb error (2) adc12sr = 0, refout = 0 f adc12clk = 2.7 mhz 2.5 adc12sr = 0, refout = 1 f adc12clk = 4.0 mhz ? 1.0 +2.0 differential e d adc12sr = 0, refout = 1 f adc12clk = 2.7 mhz 2.2 v, 3 v ? 1.0 +1.5 lsb linearity error (2) adc12sr = 0, refout = 0 f adc12clk = 2.7 mhz ? 1.0 +2.5 adc12sr = 0, refout = 1 f adc12clk = 4.0 mhz 1.0 2.0 e o offset error (3) 2.2 v, 3 v lsb adc12sr = 0, refout = 0 f adc12clk = 2.7 mhz 1.0 2.0 adc12sr = 0, refout = 1 f adc12clk = 4.0 mhz 1.0 2.0 lsb e g gain error (3) 2.2 v, 3 v adc12sr = 0, refout = 0 f adc12clk = 2.7 mhz 1.5% (4) vref adc12sr = 0, refout = 1 f adc12clk = 4.0 mhz 1.4 3.5 lsb total unadjusted e t 2.2 v, 3 v error adc12sr = 0, refout = 0 f adc12clk = 2.7 mhz 1.5% (4) vref (1) the internal reference voltage is selected by: sref2 = 0 or 1, sref1 = 1, sref0 = 1. dvref = v r+ ? v r- . (2) parameters are derived using the histogram method. (3) parameters are derived using a best fit curve. (4) the gain error and total unadjusted error are dominated by the accuracy of the integrated reference module absolute accuracy. in this mode the reference voltage used by the adc12_a is not available on a pin. copyright ? 2009 ? 2015, texas instruments incorporated specifications 41 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.39 12-bit adc, temperature sensor and built-in v mid (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit 2.2 v 680 adc12on = 1, inch = 0ah, v sensor see (2) mv t a = 0 c 3 v 680 2.2 v 2.25 tc sensor adc12on = 1, inch = 0ah mv/ c 3 v 2.25 2.2 v 100 sample time required if adc12on = 1, inch = 0ah, t sensor(sample) s channel 10 is selected (3) error of conversion result 1 lsb 3 v 100 av cc divider at channel 11, adc12on = 1, inch = 0bh 0.48 0.5 0.52 v avcc v avcc factor v mid 2.2 v 1.06 1.1 1.14 av cc divider at channel 11 adc12on = 1, inch = 0bh v 3 v 1.44 1.5 1.56 sample time required if adc12on = 1, inch = 0bh, t vmid(sample) 2.2 v, 3 v 1000 ns channel 11 is selected (4) error of conversion result 1 lsb (1) the temperature sensor is provided by the ref module. see the ref module parametric, i ref+ , regarding the current consumption of the temperature sensor. (2) the temperature sensor offset can be significant. ti recommends a single-point calibration to minimize the offset error of the built-in temperature sensor. the tlv structure contains calibration values for 30 c 3 c and 85 c 3 c for each of the available reference voltage levels. the sensor voltage can be computed as v sense = tc sensor (temperature, c) + v sensor , where tc sensor and v sensor can be computed from the calibration values for higher accuracy. see also the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ). (3) the typical equivalent impedance of the sensor is 51 k . the sample time required includes the sensor-on time t sensor(on) . (4) the on-time t vmid(on) is included in the sampling time t vmid(sample) ; no additional on time is needed. figure 5-16. typical temperature sensor voltage 42 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 ambient temperature (c) 500 550 600 650 700 750 800 850 900 950 1000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 typical temperature sensor voltage (mv)
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.40 ref, external reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit positive external reference v eref+ v eref+ > v ref ? and v eref ? (2) 1.4 av cc v voltage input negative external reference v ref ? , v eref ? v eref+ > v ref ? and v eref ? (3) 0 1.2 v voltage input (v eref+ ? differential external reference v eref+ > v ref ? and v eref ? (4) 1.4 av cc v v ref- or v eref- ) voltage input 1.4 v v eref+ v avcc , v eref ? = 0 v, f adc12clk = 5 mhz, 2.2 v, 3 v ? 26 26 a adc12shtx = 1h, conversion rate 200 ksps i veref+, i vref-, static input current veref- 1.4 v v eref+ v avcc , v eref ? = 0 v, f adc12clk = 5 mhz, 2.2 v, 3 v ? 1 1 a adc12shtx = 8h, conversion rate 20 ksps capacitance at v vref+ , v vref- c vref+ , c vref- (5) 10 f terminal (1) the external reference is used during adc conversion to charge and discharge the capacitance array. the input capacitance (c i ) is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy. (2) the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduced accuracy requirements. (3) the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with reduced accuracy requirements. (4) the accuracy limits minimum external differential reference voltage. lower differential reference voltage levels may be applied with reduced accuracy requirements. (5) two decoupling capacitors, 10 f and 100 nf, should be connected to vref to decouple the dynamic current required for an external reference source if it is used for the adc12_a. see also the msp430x5xx and msp430x6xx family user ' s guide ( slau208 ). 5.41 ref, built-in reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit refvsel = {2} for 2.5 v, 3 v 2.4625 2.50 2.5375 refon = refout = 1, i vref+ = 0 a positive built-in reference refvsel = {1} for 2.0 v, v ref+ 3 v 1.9503 1.98 2.0097 v voltage output refon = refout = 1, i vref+ = 0 a refvsel = {0} for 1.5 v, 2.2 v, 3 v 1.4677 1.49 1.5124 refon = refout = 1, i vref+ = 0 a refvsel = {0} for 1.5 v 2.2 avcc minimum voltage, av cc(min) positive built-in reference refvsel = {1} for 2.0 v 2.3 v active refvsel = {2} for 2.5 v 2.8 adc12sr = 1 (4) , refon = 1, refout = 0, 3 v 70 100 a refburst = 0 adc12sr = 1 (4) , refon = 1, refout = 1, 3 v 0.45 0.75 ma refburst = 0 operating supply current into i ref+ avcc terminal (2) (3) adc12sr = 0 (4) , refon = 1, refout = 0, 3 v 210 310 a refburst = 0 adc12sr = 0 (4) , refon = 1, refout = 1, 3 v 0.95 1.7 ma refburst = 0 (1) the reference is supplied to the adc by the ref module and is buffered locally inside the adc. the adc uses two internal buffers, one smaller and one larger for driving the vref+ terminal. when refout = 1, the reference is available at the vref+ terminal, as well as, used as the reference for the conversion and uses the larger buffer. when refout = 0, the reference is only used as the reference for the conversion and uses the smaller buffer. (2) the internal reference current is supplied by terminal avcc. consumption is independent of the adc12on control bit, unless a conversion is active. refout = 0 represents the current contribution of the smaller buffer. refout = 1 represents the current contribution of the larger buffer without external load. (3) the temperature sensor is provided by the ref module. its current is supplied via terminal avcc and is equivalent to i ref+ with refon =1 and refout = 0. (4) for devices without the adc12, the parametrics with adc12sr = 0 are applicable. copyright ? 2009 ? 2015, texas instruments incorporated specifications 43 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com ref, built-in reference (continued) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) parameter test conditions v cc min typ max unit refvsel = (0, 1, 2), load-current regulation, i vref+ = +10 a, ? 1000 a, i l(vref+) 2500 v/ma vref+ terminal (5) av cc = av cc (min) for each reference level, refvsel = (0, 1, 2), refon = refout = 1 capacitance at vref+ c vref+ refon = refout = 1 20 100 pf terminal i vref+ = 0 a, temperature coefficient of ppm/ tc ref+ refvsel = (0, 1, 2), refon = 1, 30 50 built-in reference (6) c refout = 0 or 1 av cc = av cc (min) to av cc(max) , power supply rejection ratio t a = 25 c, psrr_dc 120 300 v/v (dc) refvsel = (0, 1, 2), refon = 1, refout = 0 or 1 av cc = av cc (min) to av cc(max) , t a = 25 c, power supply rejection ratio psrr_ac f = 1 khz, vpp = 100 mv, 6.4 mv/v (ac) refvsel = (0, 1, 2), refon = 1, refout = 0 or 1 av cc = av cc (min) to av cc(max) , refvsel = (0, 1, 2), refout = 0, 75 refon = 0 1 settling time of reference t settle s av cc = av cc (min) to av cc(max) , voltage (7) c vref = c vref (max), 75 refvsel = (0, 1, 2), refout = 1, refon = 0 1 (5) contribution only due to the reference and buffer including package. this does not include resistance due to pcb trace. (6) calculated using the box method: (max( ? 40 c to 85 c) ? min( ? 40 c to 85 c)) / min( ? 40 c to 85 c)/(85 c ? ( ? 40 c)). (7) the condition is that the error in a conversion started after t refon is less than 0.5 lsb. the settling time depends on the external capacitive load when refout = 1. 44 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.42 comparator_b over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v cc supply voltage 1.8 3.6 v 1.8 v 40 cbpwrmd = 00 2.2 v 30 50 comparator operating supply i avcc_comp current into avcc, excludes 3.0 v 40 65 a reference resistor ladder cbpwrmd = 01 2.2 v, 3 v 10 30 cbpwrmd = 10 2.2 v, 3 v 0.1 0.5 quiescent current of local cbrefacc = 1, i avcc_ref reference voltage amplifier into 22 a cbreflx = 01 avcc v ic common mode input range 0 v cc ? 1 v cbpwrmd = 00 ? 20 20 v offset input offset voltage mv cbpwrmd = 01, 10 ? 10 10 c in input capacitance 5 pf on (switch closed) 3 4 k r sin series input resistance off (switch open) 30 m cbpwrmd = 00, cbf = 0 450 ns propagation delay, response t pd cbpwrmd = 01, cbf = 0 600 time cbpwrmd = 10, cbf = 0 50 s cbpwrmd = 00, cbon = 1, 0.35 0.6 1.0 cbf = 1, cbfdly = 00 cbpwrmd = 00, cbon = 1, 0.6 1.0 1.8 cbf = 1, cbfdly = 01 propagation delay with filter t pd,filter s active cbpwrmd = 00, cbon = 1, 1.0 1.8 3.4 cbf = 1, cbfdly = 10 cbpwrmd = 00, cbon = 1, 1.8 3.4 6.5 cbf = 1, cbfdly = 11 comparator enable time, cbon = 0 to cbon = 1, t en_cmp 1 2 s settling time cbpwrmd = 00, 01, 10 t en_ref resistor reference enable time cbon = 0 to cbon = 1 1 1.5 s vin vin vin reference voltage for a given vin = reference into resistor v cb_ref (n+0.5) (n+1) (n+1.5) v tap ladder (n = 0 to 31) / 32 / 32 / 32 5.43 ports pu.0 and pu.1 over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v usb = 3.3 v 10%, i oh = ? 25 ma, v oh high-level output voltage 2.4 v see figure 5-18 for typical characteristics v usb = 3.3 v 10%, i ol = 25 ma, v ol low-level output voltage 0.4 v see figure 5-17 for typical characteristics v usb = 3.3 v 10%, v ih high-level input voltage 2.0 v see figure 5-19 for typical characteristics v usb = 3.3 v 10%, v il low-level input voltage 0.8 v see figure 5-19 for typical characteristics copyright ? 2009 ? 2015, texas instruments incorporated specifications 45 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com figure 5-17. ports pu.0, pu.1 typical low-level output characteristics figure 5-18. ports pu.0, pu.1 typical high-level output characteristics figure 5-19. ports pu.0, pu.1 typical input threshold characteristics 46 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 typical pu.0, pu.1 input threshold 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.8 2.2 2.6 3 3.4 vusb supply voltage, v usb - v input threshold - v v it+ , postive-going input threshold v it- , negative-going input threshold t a = 25 c, 85 c typical high-level output current vs high-level output voltage -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.5 1 1.5 2 2.5 3 v oh - high-level output voltage - v i oh - typical high-level output current - ma v = 1.8 v t = 85 oc cc a v = 1.8 v t = 25 oc cc a v = 3.0 v t = 85 oc cc a v = 3.0 v t = 25 oc cc a typical low-level output current vs low-level output voltage 0 10 20 30 40 50 60 70 80 90 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 v ol - low-level output voltage - v i ol - typical low-level output current - ma v = 3.0 v t = 85 oc cc a v = 1.8 v t = 85 oc cc a v = 1.8 v t = 25 oc cc a v = 3.0 v t = 25 oc cc a
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.44 usb output ports dp and dm over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions min max unit v oh d+, d ? single ended usb 2.0 load conditions 2.8 3.6 v v ol d+, d ? single ended usb 2.0 load conditions 0 0.3 v z(drv) d+, d ? impedance including external series resistor of 27 28 44 full speed, differential, c l = 50 pf, t rise rise time 4 20 ns 10%/90%, rpu on d+ full speed, differential, c l = 50 pf, t fall fall time 4 20 ns 10%/90%, rpu on d+ 5.45 usb input ports dp and dm over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter min max unit v (cm) differential input common mode range 0.8 2.5 v z (in) input impedance 300 k v crs crossover voltage 1.3 2.0 v v il static se input logic low level 0.8 v v ih static se input logic high level 2.0 v vdi differential input voltage 0.2 v copyright ? 2009 ? 2015, texas instruments incorporated specifications 47 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 5.46 usb-pwr (usb power system) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit v launch v bus detection threshold 3.75 v v bus usb bus voltage normal operation 3.76 5.5 v v usb usb ldo output voltage 3.003 3.3 3.597 v v 18 internal usb voltage (1) 1.8 v maximum external current from vusb i usb_ext usb ldo is on 12 ma terminal (2) i det usb ldo current overload detection (3) 60 100 ma usb ldo is on, i suspend operating supply current into vbus terminal (4) 250 a usb pll disabled usb ldo is on, operating supply current into vbus terminal, usb 1.8-v ldo is disabled, i usb_ldo 1.8 v, 3 v 60 a represents the current of the 3.3-v ldo only v bus = 5.0 v, usbdeten = 0 or 1 usb ldo is disabled, operating supply current into vbus terminal, i vbus_dete usb 1.8-v ldo is disabled, represents the current of the vbus detection 1.8 v, 3 v 30 a ct vbus > v launch , logic usbdeten = 1 c bus vbus terminal recommended capacitance 4.7 f c usb vusb terminal recommended capacitance 220 nf c 18 v18 terminal recommended capacitance 220 nf within 2%, t enable settling time v usb and v 18 2 ms recommended capacitances rpur pullup resistance of pur terminal (5) 70 110 150 (1) this voltage is for internal uses only. no external dc loading should be applied. (2) this represents additional current that can be supplied to the application from the vusb terminal beyond the needs of the usb operation. (3) a current overload will be detected when the total current supplied from the usb ldo, including i usb_ext , exceeds this value. (4) does not include current contribution of rpu and rpd as outlined in the usb specification. (5) this value, in series with an external resistor between pur and d+, produces the rpu as outlined in the usb specification. 5.47 usb-pll (usb phase locked loop) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) parameter test conditions v cc min typ max unit i pll operating supply current 7 ma f pll pll frequency 48 mhz f upd pll reference frequency 1.5 3 mhz t lock pll lock time 2 ms t jitter pll jitter 1000 ps 48 specifications copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 5.48 flash memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) test parameter min typ max unit conditions dv cc(pgm,erase) program and erase supply voltage 1.8 3.6 v i pgm average supply current from dvcc during program (1) 3 5 ma i erase average supply current from dvcc during erase (1) 6 11 ma average supply current from dvcc during mass erase or bank i merase , i bank 6 11 ma erase (1) t cpt cumulative program time see (2) 16 ms program and erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time see (3) 64 85 s t block, 0 block program time for first byte or word see (3) 49 65 s block program time for each additional byte or word, except for last t block, 1 ? (n ? 1) see (3) 37 49 s byte or word t block, n block program time for last byte or word see (3) 55 73 s erase time for segment, mass erase, and bank erase when t erase see (3) 23 32 ms available. mclk frequency in marginal read mode f mclk,mrg 0 1 mhz (fctl4.mrg0 = 1 or fctl4.mrg1 = 1) (1) default clock system frequency of mclk = 1 mhz, aclk = 32768 hz, smclk = 1 mhz. no peripherals are enabled or active. (2) the cumulative program time must not be exceeded when writing to a 128-byte flash block. this parameter applies to all programming methods: individual word- or byte-write and block-write modes. (3) these values are hardwired into the state machine of the flash controller. 5.49 jtag and spy-bi-wire interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) test parameter min typ max unit conditions f sbw spy-bi-wire input frequency 2.2 v, 3 v 0 20 mhz t sbw,low spy-bi-wire low clock pulse duration 2.2 v, 3 v 0.025 15 s spy-bi-wire enable time (test high to acceptance of first clock t sbw, en 2.2 v, 3 v 1 s edge) (1) t sbw,rst spy-bi-wire return to normal operation time 15 100 s 2.2 v 0 5 f tck tck input frequency, 4-wire jtag (2) mhz 3 v 0 10 r internal internal pulldown resistance on test 2.2 v, 3 v 45 60 80 k (1) tools that access the spy-bi-wire interface must wait for the t sbw,en time after pulling the test/sbwtck pin high before applying the first sbwtck clock edge. (2) f tck may be restricted to meet the timing requirements of the module selected. copyright ? 2009 ? 2015, texas instruments incorporated specifications 49 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6 detailed description 6.1 cpu (link to user ' s guide) the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to- register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. the instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. each instruction can operate on word and byte data. 50 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 program counter pc/r0 stack pointer sp/r1 status register sr/cg1/r2 constant generator cg2/r3 general-purpose register r4 general-purpose register r5 general-purpose register r6 general-purpose register r7 general-purpose register r8 general-purpose register r9 general-purpose register r10 general-purpose register r11 general-purpose register r12 general-purpose register r13 general-purpose register r15 general-purpose register r14
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.2 operating modes the msp430 has one active mode and six software selectable low-power modes of operation. an interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. the following seven operating modes can be configured by software: ? active mode (am) ? all clocks are active ? low-power mode 0 (lpm0) ? cpu is disabled ? aclk and smclk remain active, mclk is disabled ? fll loop control remains active ? low-power mode 1 (lpm1) ? cpu is disabled ? fll loop control is disabled ? aclk and smclk remain active, mclk is disabled ? low-power mode 2 (lpm2) ? cpu is disabled ? mclk, fll loop control, and dcoclk are disabled ? dco dc generator remains enabled ? aclk remains active ? low-power mode 3 (lpm3) ? cpu is disabled ? mclk, fll loop control, and dcoclk are disabled ? dco dc generator is disabled ? aclk remains active ? low-power mode 4 (lpm4) ? cpu is disabled ? aclk is disabled ? mclk, fll loop control, and dcoclk are disabled ? dco dc generator is disabled ? crystal oscillator is stopped ? complete data retention ? low-power mode 4.5 (lpm4.5) ? internal regulator disabled ? no data retention ? wake-up signal from rst/nmi, p1, and p2 copyright ? 2009 ? 2015, texas instruments incorporated detailed description 51 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.3 interrupt vector addresses the interrupt vectors and the power-up start address are located in the address range 0ffffh to 0ff80h. the vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. table 6-1. interrupt sources, flags, and vectors system word interrupt source interrupt flag priority interrupt address system reset power-up external reset wdtifg, keyv (sysrstiv) (1) (2) reset 0fffeh 63, highest watchdog time-out, password violation flash memory password violation system nmi svmlifg, svmhifg, dlylifg, dlyhifg, pmm vlrlifg, vlrhifg, vmaifg, jmbnifg, (non)maskable 0fffch 62 vacant memory access jmboutifg (syssniv) (1) jtag mailbox user nmi nmi nmiifg, ofifg, accvifg, busifg (non)maskable 0fffah 61 oscillator fault (sysuniv) (1) (2) flash memory access violation comp_b comparator b interrupt flags (cbiv) (1) (3) maskable 0fff8h 60 tb0 tb0ccr0 ccifg0 (3) maskable 0fff6h 59 tb0ccr1 ccifg1 to tb0ccr6 ccifg6, tb0 maskable 0fff4h 58 tb0ifg (tb0iv) (1) (3) watchdog timer_a interval timer wdtifg maskable 0fff2h 57 mode usci_a0 receive or transmit uca0rxifg, uca0txifg (uca0iv) (1) (3) maskable 0fff0h 56 usci_b0 receive or transmit ucb0rxifg, ucb0txifg (ucb0iv) (1) (3) maskable 0ffeeh 55 adc12_a adc12ifg0 to adc12ifg15 (adc12iv) (1) (3) (4) maskable 0ffech 54 ta0 ta0ccr0 ccifg0 (3) maskable 0ffeah 53 ta0ccr1 ccifg1 to ta0ccr4 ccifg4, ta0 maskable 0ffe8h 52 ta0ifg (ta0iv) (1) (3) usb_ubm usb interrupts (usbiv) (1) (3) maskable 0ffe6h 51 dma dma0ifg, dma1ifg, dma2ifg (dmaiv) (1) (3) maskable 0ffe4h 50 ta1 ta1ccr0 ccifg0 (3) maskable 0ffe2h 49 ta1ccr1 ccifg1 to ta1ccr2 ccifg2, ta1 maskable 0ffe0h 48 ta1ifg (ta1iv) (1) (3) i/o port p1 p1ifg.0 to p1ifg.7 (p1iv) (1) (3) maskable 0ffdeh 47 usci_a1 receive or transmit uca1rxifg, uca1txifg (uca1iv) (1) (3) maskable 0ffdch 46 usci_b1 receive or transmit ucb1rxifg, ucb1txifg (ucb1iv) (1) (3) maskable 0ffdah 45 ta2 ta2ccr0 ccifg0 (3) maskable 0ffd8h 44 ta2ccr1 ccifg1 to ta2ccr2 ccifg2, ta2 maskable 0ffd6h 43 ta2ifg (ta2iv) (1) (3) i/o port p2 p2ifg.0 to p2ifg.7 (p2iv) (1) (3) maskable 0ffd4h 42 rtcrdyifg, rtctevifg, rtcaifg, rtc_a maskable 0ffd2h 41 rt0psifg, rt1psifg (rtciv) (1) (3) 0ffd0h 40 reserved reserved (5) ? ? 0ff80h 0, lowest (1) multiple source flags (2) a reset is generated if the cpu tries to fetch instructions from within peripheral space or vacant memory space. (non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) interrupt flags are located in the module. (4) only on devices with adc, otherwise reserved. (5) reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. to maintain compatibility with other devices, ti recommends reserving these locations. 52 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.4 memory organization table 6-2. memory organization (1) msp430f5525 msp430f5522 msp430f5527 msp430f5529 msp430f5524 msp430f5521 msp430f5526 msp430f5528 msp430f5515 msp430f5513 msp430f5517 msp430f5519 msp430f5514 memory (flash) total size 32kb 64kb 96kb 128kb main: interrupt vector 00ffffh ? 00ff80h 00ffffh ? 00ff80h 00ffffh ? 00ff80h 00ffffh ? 00ff80h n/a n/a n/a 32kb bank d 0243ffh ? 01c400h n/a n/a 32kb 32kb bank c 01c3ffh ? 014400h 01c3ffh ? 014400h main: code memory 15kb 32kb 32kb 32kb bank b 00ffffh ? 00c400h 0143ffh ? 00c400h 0143ffh ? 00c400h 0143ffh ? 00c400h 17kb 32kb 32kb 32kb bank a 00c3ffh ? 008000h 00c3ffh ? 004400h 00c3ffh ? 004400h 00c3ffh ? 004400h sector 3 2kb (2) n/a n/a 2kb 0043ffh ? 003c00h 0043ffh ? 003c00h sector 2 2kb (3) n/a 2kb 2kb 003bffh ? 003400h 003bffh ? 003400h 003bffh ? 003400h ram sector 1 2kb 2kb 2kb 2kb 0033ffh ? 002c00h 0033ffh ? 002c00h 0033ffh ? 002c00h 0033ffh ? 002c00h sector 0 2kb 2kb 2kb 2kb 002bffh ? 002400h 002bffh ? 002400h 002bffh ? 002400h 002bffh ? 002400h sector 7 2kb 2kb 2kb 2kb usb ram (4) 0023ffh ? 001c00h 0023ffh ? 001c00h 0023ffh ? 001c00h 0023ffh ? 001c00h info a 128 b 128 b 128 b 128 b 0019ffh ? 001980h 0019ffh ? 001980h 0019ffh ? 001980h 0019ffh ? 001980h info b 128 b 128 b 128 b 128 b 00197fh ? 001900h 00197fh ? 001900h 00197fh ? 001900h 00197fh ? 001900h information memory (flash) info c 128 b 128 b 128 b 128 b 0018ffh ? 001880h 0018ffh ? 001880h 0018ffh ? 001880h 0018ffh ? 001880h info d 128 b 128 b 128 b 128 b 00187fh ? 001800h 00187fh ? 001800h 00187fh ? 001800h 00187fh ? 001800h bsl 3 512 b 512 b 512 b 512 b 0017ffh ? 001600h 0017ffh ? 001600h 0017ffh ? 001600h 0017ffh ? 001600h bsl 2 512 b 512 b 512 b 512 b 0015ffh ? 001400h 0015ffh ? 001400h 0015ffh ? 001400h 0015ffh ? 001400h bootstrap loader (bsl) memory (flash) bsl 1 512 b 512 b 512 b 512 b 0013ffh ? 001200h 0013ffh ? 001200h 0013ffh ? 001200h 0013ffh ? 001200h bsl 0 512 b 512 b 512 b 512 b 0011ffh ? 001000h 0011ffh ? 001000h 0011ffh ? 001000h 0011ffh ? 001000h size 4kb 4kb 4kb 4kb peripherals 000fffh ? 0h 000fffh ? 0h 000fffh ? 0h 000fffh ? 0h (1) n/a = not available (2) msp430f5522 only (3) msp430f5522, msp430f5521 only (4) usb ram can be used as general purpose ram when not used for usb operation. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 53 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.5 bootstrap loader (bsl) the bsl enables users to program the flash memory or ram using various serial interfaces. access to the device memory by the bsl is protected by an user-defined password. for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user's guide ( slau278 ). for complete description of the features of the bsl and its implementation, see the msp430 programming via the bootstrap loader user's guide ( slau319 ). 6.5.1 usb bsl all devices come preprogrammed with the usb bsl. use of the usb bsl requires external access to the six pins shown in table 6-3 . in addition to these pins, the application must support external components necessary for normal usb operation; for example, the proper crystal on xt2in and xt2out, proper decoupling, and so on. table 6-3. usb bsl pin requirements and functions device signal bsl function pu.0/dp usb data terminal dp pu.1/dm usb data terminal dm pur usb pullup resistor terminal vbus usb bus power supply vssu usb ground supply note the default usb bsl evaluates the logic level of the pur pin after a bor reset. if the pur pin is pulled high externally, then the bsl is invoked. therefore, unless the application is invoking the bsl, it is important to keep pur pulled low after a bor reset, even if bsl or usb is never used. ti recommends applying a 1-m resistor to ground. 6.5.2 uart bsl a uart bsl is also available that can be programmed by the user into the bsl memory by replacing the preprogrammed, factory supplied, usb bsl. use of the uart bsl requires external access to the six pins shown in table 6-4 . table 6-4. uart bsl pin requirements and functions device signal bsl function rst/nmi/sbwtdio entry sequence signal test/sbwtck entry sequence signal p1.1 data transmit p1.2 data receive vcc power supply vss ground supply 54 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.6 jtag operation 6.6.1 jtag standard interface the msp430 family supports the standard jtag interface which requires four signals for sending and receiving data. the jtag signals are shared with general-purpose i/o. the test/sbwtck pin is used to enable the jtag signals. in addition to these signals, the rst/nmi/sbwtdio is required to interface with msp430 development tools and device programmers. the jtag pin requirements are shown in table 6- 5 . for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user's guide ( slau278 ). for a complete description of the features of the jtag interface and its implementation, see msp430 programming via the jtag interface ( slau320 ). table 6-5. jtag pin requirements and functions device signal direction function pj.3/tck in jtag clock input pj.2/tms in jtag state control pj.1/tdi/tclk in jtag data input, tclk input pj.0/tdo out jtag data output test/sbwtck in enable jtag pins rst/nmi/sbwtdio in external reset vcc power supply vss ground supply 6.6.2 spy-bi-wire interface in addition to the standard jtag interface, the msp430 family supports the two wire spy-bi-wire interface. spy-bi-wire can be used to interface with msp430 development tools and device programmers. the spy-bi-wire interface pin requirements are shown in table 6-6 . for further details on interfacing to development tools and device programmers, see the msp430 hardware tools user's guide ( slau278 ). for a complete description of the features of the jtag interface and its implementation, see msp430 programming via the jtag interface ( slau320 ). table 6-6. spy-bi-wire pin requirements and functions device signal direction function test/sbwtck in spy-bi-wire clock input rst/nmi/sbwtdio in, out spy-bi-wire data input/output vcc power supply vss ground supply copyright ? 2009 ? 2015, texas instruments incorporated detailed description 55 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.7 flash memory (link to user ' s guide) the flash memory can be programmed through the jtag port, spy-bi-wire (sbw), the bsl, or in-system by the cpu. the cpu can perform single-byte, single-word, and long-word writes to the flash memory. features of the flash memory include: ? flash memory has n segments of main memory and four segments of information memory (a to d) of 128 bytes each. each segment in main memory is 512 bytes in size. ? segments 0 to n may be erased in one step, or each segment may be individually erased. ? segments a to d can be erased individually. segments a to d are also called information memory . ? segment a can be locked separately. 6.8 ram (link to user ' s guide) the ram is made up of n sectors. each sector can be completely powered down to save leakage; however; all data is lost. features of the ram include: ? ram has n sectors. the size of a sector can be found in section 6.4 . ? each sector 0 to n can be complete disabled; however, data retention is lost. ? each sector 0 to n automatically enters low-power retention mode when possible. ? for devices that contain usb memory, the usb memory can be used as normal ram if usb is not required. 6.9 peripherals peripherals are connected to the cpu through data, address, and control buses. peripherals can be handled using all instructions. for complete module descriptions, see the msp430x5xx and msp430x6xx family user's guide ( slau208 ). 6.9.1 digital i/o (link to user ' s guide) there are up to eight 8-bit i/o ports implemented: for 80 pin options, p1, p2, p3, p4, p5, p6, and p7 are complete, and p8 is reduced to 3-bit i/o. for 64 pin options, p3 and p5 are reduced to 5-bit i/o and 6-bit i/o, respectively, and p7 and p8 are completely removed. port pj contains four individual i/o ports, common to all devices. ? all individual i/o bits are independently programmable. ? any combination of input, output, and interrupt conditions is possible. ? pullup or pulldown on all ports is programmable. ? drive strength on all ports is programmable. ? edge-selectable interrupt and lpm4.5 wakeup input capability is available for all bits of ports p1 and p2. ? read and write access to port-control registers is supported by all instructions. ? ports can be accessed byte-wise (p1 through p8) or word-wise in pairs (pa through pd). 56 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.9.2 port mapping controller (link to user ' s guide) the port mapping controller allows the flexible and reconfigurable mapping of digital functions to port p4 (see table 6-7 ). table 6-8 shows the default mappings. table 6-7. port mapping mnemonics and functions value pxmapy mnemonic input pin function output pin function 0 pm_none none dvss pm_cbout0 - comparator_b output 1 pm_tb0clk tb0 clock input pm_adc12clk - adc12clk 2 pm_dmae0 dmae0 input pm_svmout - svm output 3 pm_tb0outh tb0 high impedance input tb0outh 4 pm_tb0ccr0a tb0 ccr0 capture input cci0a tb0 ccr0 compare output out0 5 pm_tb0ccr1a tb0 ccr1 capture input cci1a tb0 ccr1 compare output out1 6 pm_tb0ccr2a tb0 ccr2 capture input cci2a tb0 ccr2 compare output out2 7 pm_tb0ccr3a tb0 ccr3 capture input cci3a tb0 ccr3 compare output out3 8 pm_tb0ccr4a tb0 ccr4 capture input cci4a tb0 ccr4 compare output out4 9 pm_tb0ccr5a tb0 ccr5 capture input cci5a tb0 ccr5 compare output out5 10 pm_tb0ccr6a tb0 ccr6 capture input cci6a tb0 ccr6 compare output out6 pm_uca1rxd usci_a1 uart rxd (direction controlled by usci ? input) 11 pm_uca1somi usci_a1 spi slave out master in (direction controlled by usci) pm_uca1txd usci_a1 uart txd (direction controlled by usci ? output) 12 pm_uca1simo usci_a1 spi slave in master out (direction controlled by usci) pm_uca1clk usci_a1 clock input/output (direction controlled by usci) 13 pm_ucb1ste usci_b1 spi slave transmit enable (direction controlled by usci) pm_ucb1somi usci_b1 spi slave out master in (direction controlled by usci) 14 pm_ucb1scl usci_b1 i 2 c clock (open drain and direction controlled by usci) pm_ucb1simo usci_b1 spi slave in master out (direction controlled by usci) 15 pm_ucb1sda usci_b1 i 2 c data (open drain and direction controlled by usci) pm_ucb1clk usci_b1 clock input/output (direction controlled by usci) 16 pm_uca1ste usci_a1 spi slave transmit enable (direction controlled by usci) 17 pm_cbout1 none comparator_b output 18 pm_mclk none mclk 19 - 30 reserved none dvss disables the output driver and the input schmitt-trigger to prevent parasitic 31 (0ffh) (1) pm_analog cross currents when applying analog signals. (1) the value of the pm_analog mnemonic is set to 0ffh. the port mapping registers are only 5 bits wide and the upper bits are ignored resulting in a read out value of 31. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 57 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-8. default mapping pin pxmapy mnemonic input pin function output pin function usci_b1 spi slave transmit enable (direction controlled by usci) p4.0/p4map0 pm_ucb1ste/pm_uca1clk usci_a1 clock input/output (direction controlled by usci) usci_b1 spi slave in master out (direction controlled by usci) p4.1/p4map1 pm_ucb1simo/pm_ucb1sda usci_b1 i 2 c data (open drain and direction controlled by usci) usci_b1 spi slave out master in (direction controlled by usci) p4.2/p4map2 pm_ucb1somi/pm_ucb1scl usci_b1 i 2 c clock (open drain and direction controlled by usci) usci_a1 spi slave transmit enable (direction controlled by usci) p4.3/p4map3 pm_ucb1clk/pm_uca1ste usci_b1 clock input/output (direction controlled by usci) usci_a1 uart txd (direction controlled by usci ? output) p4.4/p4map4 pm_uca1txd/pm_uca1simo usci_a1 spi slave in master out (direction controlled by usci) usci_a1 uart rxd (direction controlled by usci ? input) p4.5/p4map5 pm_uca1rxd/pm_uca1somi usci_a1 spi slave out master in (direction controlled by usci) p4.6/p4map6 pm_none none dvss p4.7/p4map7 pm_none none dvss 6.9.3 oscillator and system clock (link to user ' s guide) the clock system in the msp430f552x and msp430f551x family of devices is supported by the unified clock system (ucs) module that includes support for a 32-khz watch crystal oscillator (xt1 lf mode) (xt1 hf mode is not supported), an internal very-low-power low-frequency oscillator (vlo), an internal trimmed low-frequency oscillator (refo), an integrated internal digitally controlled oscillator (dco), and a high-frequency crystal oscillator (xt2). the ucs module is designed to meet the requirements of both low system cost and low power consumption. the ucs module features digital frequency locked loop (fll) hardware that, in conjunction with a digital modulator, stabilizes the dco frequency to a programmable multiple of the selected fll reference frequency. the internal dco provides a fast turnon clock source and stabilizes in 3.5 s (typical). the ucs module provides the following clock signals: ? auxiliary clock (aclk), sourced from a 32-khz watch crystal (xt1), a high-frequency crystal (xt2), the internal low-frequency oscillator (vlo), the trimmed low-frequency oscillator (refo), or the internal digitally controlled oscillator dco. ? main clock (mclk), the system clock used by the cpu. mclk can be sourced by same sources made available to aclk. ? sub-main clock (smclk), the subsystem clock used by the peripheral modules. smclk can be sourced by same sources made available to aclk. ? aclk/n, the buffered output of aclk, aclk/2, aclk/4, aclk/8, aclk/16, aclk/32. 6.9.4 power management module (pmm) (link to user ' s guide) the pmm includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. the pmm also includes supply voltage supervisor (svs) and supply voltage monitoring (svm) circuitry, as well as brownout protection. the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. the svs and svm circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (svs) (the device is automatically reset) and supply voltage monitoring (svm) (the device is not automatically reset). svs and svm circuitry is available on the primary supply and core supply. 6.9.5 hardware multiplier (link to user ' s guide) the multiplication operation is supported by a dedicated peripheral module. the module performs operations with 32-, 24-, 16-, and 8-bit operands. the module supports signed and unsigned multiplication as well as signed and unsigned multiply-and-accumulate operations. 58 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.9.6 real-time clock (rtc_a) (link to user ' s guide) the rtc_a module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (rtc) (calendar mode). in counter mode, the rtc_a also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. both timers can be read and written by software. calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. the rtc_a also supports flexible alarm functions and offset- calibration hardware. 6.9.7 watchdog timer (wdt_a) (link to user ' s guide) the primary function of the wdt_a module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. 6.9.8 system module (sys) (link to user ' s guide) the sys module handles many of the system functions within the device. these include power-on reset and power-up clear handling, nmi source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). it also includes a data exchange mechanism through jtag called a jtag mailbox that can be used in the application. table 6-9. system module interrupt vector registers interrupt vector register address interrupt event value priority 019eh no interrupt pending 00h brownout (bor) 02h highest rst/nmi (por) 04h pmmswbor (bor) 06h wakeup from lpmx.5 08h security violation (bor) 0ah svsl (por) 0ch svsh (por) 0eh svml_ovp (por) 10h sysrstiv, system reset svmh_ovp (por) 12h pmmswpor (por) 14h wdt time-out (puc) 16h wdt password violation (puc) 18h keyv flash password violation (puc) 1ah reserved 1ch peripheral area fetch (puc) 1eh pmm password violation (puc) 20h reserved 22h to 3eh lowest copyright ? 2009 ? 2015, texas instruments incorporated detailed description 59 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-9. system module interrupt vector registers (continued) interrupt vector register address interrupt event value priority 019ch no interrupt pending 00h svmlifg 02h highest svmhifg 04h svsmldlyifg 06h svsmhdlyifg 08h syssniv, system nmi vmaifg 0ah jmbinifg 0ch jmboutifg 0eh svmlvlrifg 10h svmhvlrifg 12h reserved 14h to 1eh lowest 019ah no interrupt pending 00h nmiifg 02h highest ofifg 04h sysuniv, user nmi accvifg 06h busifg 08h reserved 0ah to 1eh lowest 6.9.9 dma controller (link to user ' s guide) the dma controller allows movement of data from one memory address to another without cpu intervention. for example, the dma controller can be used to move data from the adc12_a conversion memory to ram. using the dma controller can increase the throughput of peripheral modules. the dma controller reduces system power consumption by allowing the cpu to remain in sleep mode, without having to awaken to move data to or from a peripheral. the usb timestamp generator also uses the dma trigger assignments described in table 6-10 . table 6-10. dma trigger assignments (1) channel trigger 0 1 2 0 dmareq dmareq dmareq 1 ta0ccr0 ccifg ta0ccr0 ccifg ta0ccr0 ccifg 2 ta0ccr2 ccifg ta0ccr2 ccifg ta0ccr2 ccifg 3 ta1ccr0 ccifg ta1ccr0 ccifg ta1ccr0 ccifg 4 ta1ccr2 ccifg ta1ccr2 ccifg ta1ccr2 ccifg 5 ta2ccr0 ccifg ta2ccr0 ccifg ta2ccr0 ccifg 6 ta2ccr2 ccifg ta2ccr2 ccifg ta2ccr2 ccifg 7 tb0ccr0 ccifg tb0ccr0 ccifg tb0ccr0 ccifg 8 tb0ccr2 ccifg tb0ccr2 ccifg tb0ccr2 ccifg 9 reserved reserved reserved 10 reserved reserved reserved 11 reserved reserved reserved 12 reserved reserved reserved 13 reserved reserved reserved 14 reserved reserved reserved 15 reserved reserved reserved (1) if a reserved trigger source is selected, no trigger1 is generated. 60 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-10. dma trigger assignments (1) (continued) channel trigger 0 1 2 16 uca0rxifg uca0rxifg uca0rxifg 17 uca0txifg uca0txifg uca0txifg 18 ucb0rxifg ucb0rxifg ucb0rxifg 19 ucb0txifg ucb0txifg ucb0txifg 20 uca1rxifg uca1rxifg uca1rxifg 21 uca1txifg uca1txifg uca1txifg 22 ucb1rxifg ucb1rxifg ucb1rxifg 23 ucb1txifg ucb1txifg ucb1txifg 24 adc12ifgx (2) adc12ifgx (2) adc12ifgx (2) 25 reserved reserved reserved 26 reserved reserved reserved 27 usb fnrxd usb fnrxd usb fnrxd 28 usb ready usb ready usb ready 29 mpy ready mpy ready mpy ready 30 dma2ifg dma0ifg dma1ifg 31 dmae0 dmae0 dmae0 (2) only on devices with adc. reserved on devices without adc. 6.9.10 universal serial communication interface (usci) (links to user ' s guide: uart mode , spi mode , i 2 c mode ) the usci modules are used for serial data communication. the usci module supports synchronous communication protocols such as spi (3-pin or 4-pin) and i 2 c, and asynchronous communication protocols such as uart, enhanced uart with automatic baudrate detection, and irda. each usci module contains two portions, a and b. the usci_an module provides support for spi (3-pin or 4-pin), uart, enhanced uart, or irda. the usci_bn module provides support for spi (3-pin or 4-pin) or i 2 c. the msp430f55xx series includes two complete usci modules (n = 0, 1). copyright ? 2009 ? 2015, texas instruments incorporated detailed description 61 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.9.11 ta0 (link to user ' s guide) ta0 is a 16-bit timer and counter (timer_a type) with five capture/compare registers. it can support multiple capture/compare registers, pwm outputs, and interval timing. it also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-11. ta0 signal connections input pin number output pin number device module module device module input input output output rgc, yff, block pn rgc, yff, zqe pn signal signal signal signal zqe 18, h2-p1.0 21-p1.0 ta0clk taclk aclk aclk (internal) timer na na smclk smclk (internal) 18, h2-p1.0 21-p1.0 ta0clk taclk 19, h3-p1.1 22-p1.1 ta0.0 cci0a 19, h3-p1.1 22-p1.1 dv ss cci0b ccr0 ta0 ta0.0 dv ss gnd dv cc v cc 20, j3-p1.2 23-p1.2 ta0.1 cci1a 20, j3-p1.2 23-p1.2 adc12 adc12 cbout (internal) (1) (internal) (1) cci1b (internal) adc12shsx = adc12shsx = ccr1 ta1 ta0.1 {1} {1} dv ss gnd dv cc v cc 21, g4-p1.3 24-p1.3 ta0.2 cci2a 21, g4-p1.3 24-p1.3 aclk cci2b (internal) ccr2 ta2 ta0.2 dv ss gnd dv cc v cc 22, h4-p1.4 25-p1.4 ta0.3 cci3a 22, h4-p1.4 25-p1.4 dv ss cci3b ccr3 ta3 ta0.3 dv ss gnd dv cc v cc 23, j4-p1.5 26-p1.5 ta0.4 cci4a 23, j4-p1.5 26-p1.5 dv ss cci4b ccr4 ta4 ta0.4 dv ss gnd dv cc v cc (1) only on devices with adc. 62 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.9.12 ta1 (link to user ' s guide) ta1 is a 16-bit timer and counter (timer_a type) with three capture/compare registers. it can support multiple capture/compare registers, pwm outputs, and interval timing. it also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-12. ta1 signal connections input pin number output pin number device module module device module input input output output rgc, yff, rgc, yff, block pn pn signal signal signal signal zqe zqe 24, g5-p1.6 27-p1.6 ta1clk taclk aclk aclk (internal) timer na na smclk smclk (internal) 24, g5-p1.6 27-p1.6 ta1clk taclk 25, h5-p1.7 28-p1.7 ta1.0 cci0a 25, h5-p1.7 28-p1.7 dv ss cci0b ccr0 ta0 ta1.0 dv ss gnd dv cc v cc 26, j5-p2.0 29-p2.0 ta1.1 cci1a 26, j5-p2.0 29-p2.0 cbout cci1b (internal) ccr1 ta1 ta1.1 dv ss gnd dv cc v cc 27, g6-p2.1 30-p2.1 ta1.2 cci2a 27, g6-p2.1 30-p2.1 aclk cci2b (internal) ccr2 ta2 ta1.2 dv ss gnd dv cc v cc copyright ? 2009 ? 2015, texas instruments incorporated detailed description 63 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.9.13 ta2 (link to user ' s guide) ta2 is a 16-bit timer and counter (timer_a type) with three capture/compare registers. it can support multiple capture/compare registers, pwm outputs, and interval timing. it also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-13. ta2 signal connections input pin number output pin number device module module device module input input output output rgc, yff, rgc, yff, block pn pn signal signal signal signal zqe zqe 28, j6-p2.2 31-p2.2 ta2clk taclk aclk aclk (internal) timer na na smclk smclk (internal) 28, j6-p2.2 31-p2.2 ta2clk taclk 29, h6-p2.3 32-p2.3 ta2.0 cci0a 29, h6-p2.3 32-p2.3 dv ss cci0b ccr0 ta0 ta2.0 dv ss gnd dv cc v cc 30, j7-p2.4 33-p2.4 ta2.1 cci1a 30, j7-p2.4 33-p2.4 cbout cci1b (internal) ccr1 ta1 ta2.1 dv ss gnd dv cc v cc 31, j8-p2.5 34-p2.5 ta2.2 cci2a 31, j8-p2.5 34-p2.5 aclk cci2b (internal) ccr2 ta2 ta2.2 dv ss gnd dv cc v cc 64 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.9.14 tb0 (link to user ' s guide) tb0 is a 16-bit timer and counter (timer_b type) with seven capture/compare registers. it can support multiple capture/compare registers, pwm outputs, and interval timing. it also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. table 6-14. tb0 signal connections input pin number output pin number device module module device module input input output output rgc, yff, rgc, yff, block pn pn signal signal signal signal zqe (1) zqe (1) 60-p7.7 tb0clk tbclk aclk aclk (internal) timer na na smclk smclk (internal) 60-p7.7 tb0clk tbclk 55-p5.6 tb0.0 cci0a 55-p5.6 adc12 adc12 (internal) (2) (internal) (2) 55-p5.6 tb0.0 cci0b adc12shsx = adc12shsx = ccr0 tb0 tb0.0 {2} {2} dv ss gnd dv cc v cc 56-p5.7 tb0.1 cci1a 56-p5.7 adc12 (internal) adc12 (internal) cbout cci1b adc12shsx = adc12shsx = (internal) ccr1 tb1 tb0.1 {3} {3} dv ss gnd dv cc v cc 57-p7.4 tb0.2 cci2a 57-p7.4 57-p7.4 tb0.2 cci2b ccr2 tb2 tb0.2 dv ss gnd dv cc v cc 58-p7.5 tb0.3 cci3a 58-p7.5 58-p7.5 tb0.3 cci3b ccr3 tb3 tb0.3 dv ss gnd dv cc v cc 59-p7.6 tb0.4 cci4a 59-p7.6 59-p7.6 tb0.4 cci4b ccr4 tb4 tb0.4 dv ss gnd dv cc v cc 42-p3.5 tb0.5 cci5a 42-p3.5 42-p3.5 tb0.5 cci5b ccr5 tb5 tb0.5 dv ss gnd dv cc v cc 43-p3.6 tb0.6 cci6a 43-p3.6 aclk cci6b (internal) ccr6 tb6 tb0.6 dv ss gnd dv cc v cc (1) timer functions are selectable through the port mapping controller. (2) only on devices with adc copyright ? 2009 ? 2015, texas instruments incorporated detailed description 65 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.9.15 comparator_b (link to user ' s guide) the primary function of the comparator_b module is to support precision slope analog-to-digital conversions, battery voltage supervision, and monitoring of external analog signals. 6.9.16 adc12_a (link to user ' s guide) the adc12_a module supports fast 12-bit analog-to-digital conversions. the module implements a 12-bit sar core, sample select control, reference generator and a 16 word conversion-and-control buffer. the conversion-and-control buffer allows up to 16 independent adc samples to be converted and stored without any cpu intervention. 6.9.17 crc16 (link to user ' s guide) the crc16 module produces a signature based on a sequence of entered data values and can be used for data checking purposes. the crc16 module signature is based on the crc-ccitt standard. 6.9.18 ref voltage reference (link to user ' s guide) the reference module (ref) is responsible for generation of all critical reference voltages that can be used by the various analog peripherals in the device. 6.9.19 universal serial bus (usb) (link to user ' s guide) the usb module is a fully integrated usb interface that is compliant with the usb 2.0 specification. the module supports full-speed operation of control, interrupt, and bulk transfers. the module includes an integrated ldo, phy, and pll. the pll is highly-flexible and can support a wide range of input clock frequencies. usb ram, when not used for usb communication, can be used by the system. 6.9.20 embedded emulation module (eem) (link to user ' s guide) the eem supports real-time in-system debugging. the l version of the eem has the following features: ? eight hardware triggers or breakpoints on memory access ? two hardware triggers or breakpoints on cpu register write access ? up to 10 hardware triggers can be combined to form complex triggers or breakpoints ? two cycle counters ? sequencer ? state storage ? clock control on module level 66 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.9.21 peripheral file map table 6-15 lists the base address for the registers of each module. the following tables list the offsets for all available registers in each module. table 6-15. peripherals offset address module name base address range special functions (see table 6-16 ) 0100h 000h-01fh pmm (see table 6-17 ) 0120h 000h-010h flash control (see table 6-18 ) 0140h 000h-00fh crc16 (see table 6-19 ) 0150h 000h-007h ram control (see table 6-20 ) 0158h 000h-001h watchdog (see table 6-21 ) 015ch 000h-001h ucs (see table 6-22 ) 0160h 000h-01fh sys (see table 6-23 ) 0180h 000h-01fh shared reference (see table 6-24 ) 01b0h 000h-001h port mapping control (see table 6-25 ) 01c0h 000h-002h port mapping port p4 (see table 6-25 ) 01e0h 000h-007h port p1 and p2 (see table 6-26 ) 0200h 000h-01fh port p3 and p4 (see table 6-27 ) 0220h 000h-00bh port p5 and p6 (see table 6-28 ) 0240h 000h-00bh port p7 and p8 (see table 6-29 ) 0260h 000h-00bh port pj (see table 6-30 ) 0320h 000h-01fh ta0 (see table 6-31 ) 0340h 000h-02eh ta1 (see table 6-32 ) 0380h 000h-02eh tb0 (see table 6-33 ) 03c0h 000h-02eh ta2 (see table 6-34 ) 0400h 000h-02eh real-time clock (rtc_a) (see table 6-35 ) 04a0h 000h-01bh 32-bit hardware multiplier (see table 6-36 ) 04c0h 000h-02fh dma general control (see table 6-37 ) 0500h 000h-00fh dma channel 0 (see table 6-37 ) 0510h 000h-00ah dma channel 1 (see table 6-37 ) 0520h 000h-00ah dma channel 2 (see table 6-37 ) 0530h 000h-00ah usci_a0 (see table 6-38 ) 05c0h 000h-01fh usci_b0 (see table 6-39 ) 05e0h 000h-01fh usci_a1 (see table 6-40 ) 0600h 000h-01fh usci_b1 (see table 6-41 ) 0620h 000h-01fh adc12_a (see table 6-42 ) 0700h 000h-03eh comparator_b (see table 6-43 ) 08c0h 000h-00fh usb configuration (see table 6-44 ) 0900h 000h-014h usb control (see table 6-45 ) 0920h 000h-01fh copyright ? 2009 ? 2015, texas instruments incorporated detailed description 67 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-16. special function registers (base address: 0100h) register description register offset sfr interrupt enable sfrie1 00h sfr interrupt flag sfrifg1 02h sfr reset pin control sfrrpcr 04h table 6-17. pmm registers (base address: 0120h) register description register offset pmm control 0 pmmctl0 00h pmm control 1 pmmctl1 02h svs high side control svsmhctl 04h svs low side control svsmlctl 06h pmm interrupt flags pmmifg 0ch pmm interrupt enable pmmie 0eh pmm power mode 5 control pm5ctl0 10h table 6-18. flash control registers (base address: 0140h) register description register offset flash control 1 fctl1 00h flash control 3 fctl3 04h flash control 4 fctl4 06h table 6-19. crc16 registers (base address: 0150h) register description register offset crc data input crc16di 00h crc data input reverse byte crcdirb 02h crc initialization and result crcinires 04h crc result reverse byte crcresr 06h table 6-20. ram control registers (base address: 0158h) register description register offset ram control 0 rcctl0 00h table 6-21. watchdog registers (base address: 015ch) register description register offset watchdog timer control wdtctl 00h table 6-22. ucs registers (base address: 0160h) register description register offset ucs control 0 ucsctl0 00h ucs control 1 ucsctl1 02h ucs control 2 ucsctl2 04h ucs control 3 ucsctl3 06h ucs control 4 ucsctl4 08h ucs control 5 ucsctl5 0ah ucs control 6 ucsctl6 0ch ucs control 7 ucsctl7 0eh 68 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-22. ucs registers (base address: 0160h) (continued) register description register offset ucs control 8 ucsctl8 10h table 6-23. sys registers (base address: 0180h) register description register offset system control sysctl 00h bootstrap loader configuration area sysbslc 02h jtag mailbox control sysjmbc 06h jtag mailbox input 0 sysjmbi0 08h jtag mailbox input 1 sysjmbi1 0ah jtag mailbox output 0 sysjmbo0 0ch jtag mailbox output 1 sysjmbo1 0eh bus error vector generator sysberriv 18h user nmi vector generator sysuniv 1ah system nmi vector generator syssniv 1ch reset vector generator sysrstiv 1eh table 6-24. shared reference registers (base address: 01b0h) register description register offset shared reference control refctl 00h table 6-25. port mapping registers (base address of port mapping control: 01c0h, port p4: 01e0h) register description register offset port mapping key and id register pmapkeyid 00h port mapping control register pmapctl 02h port p4.0 mapping register p4map0 00h port p4.1 mapping register p4map1 01h port p4.2 mapping register p4map2 02h port p4.3 mapping register p4map3 03h port p4.4 mapping register p4map4 04h port p4.5 mapping register p4map5 05h port p4.6 mapping register p4map6 06h port p4.7 mapping register p4map7 07h copyright ? 2009 ? 2015, texas instruments incorporated detailed description 69 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-26. port p1 and p2 registers (base address: 0200h) register description register offset port p1 input p1in 00h port p1 output p1out 02h port p1 direction p1dir 04h port p1 pullup or pulldown enable p1ren 06h port p1 drive strength p1ds 08h port p1 selection p1sel 0ah port p1 interrupt vector word p1iv 0eh port p1 interrupt edge select p1ies 18h port p1 interrupt enable p1ie 1ah port p1 interrupt flag p1ifg 1ch port p2 input p2in 01h port p2 output p2out 03h port p2 direction p2dir 05h port p2 pullup or pulldown enable p2ren 07h port p2 drive strength p2ds 09h port p2 selection p2sel 0bh port p2 interrupt vector word p2iv 1eh port p2 interrupt edge select p2ies 19h port p2 interrupt enable p2ie 1bh port p2 interrupt flag p2ifg 1dh table 6-27. port p3 and p4 registers (base address: 0220h) register description register offset port p3 input p3in 00h port p3 output p3out 02h port p3 direction p3dir 04h port p3 pullup or pulldown enable p3ren 06h port p3 drive strength p3ds 08h port p3 selection p3sel 0ah port p4 input p4in 01h port p4 output p4out 03h port p4 direction p4dir 05h port p4 pullup or pulldown enable p4ren 07h port p4 drive strength p4ds 09h port p4 selection p4sel 0bh 70 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-28. port p5 and p6 registers (base address: 0240h) register description register offset port p5 input p5in 00h port p5 output p5out 02h port p5 direction p5dir 04h port p5 pullup or pulldown enable p5ren 06h port p5 drive strength p5ds 08h port p5 selection p5sel 0ah port p6 input p6in 01h port p6 output p6out 03h port p6 direction p6dir 05h port p6 pullup or pulldown enable p6ren 07h port p6 drive strength p6ds 09h port p6 selection p6sel 0bh table 6-29. port p7 and p8 registers (base address: 0260h) register description register offset port p7 input p7in 00h port p7 output p7out 02h port p7 direction p7dir 04h port p7 pullup or pulldown enable p7ren 06h port p7 drive strength p7ds 08h port p7 selection p7sel 0ah port p8 input p8in 01h port p8 output p8out 03h port p8 direction p8dir 05h port p8 pullup or pulldown enable p8ren 07h port p8 drive strength p8ds 09h port p8 selection p8sel 0bh table 6-30. port j registers (base address: 0320h) register description register offset port pj input pjin 00h port pj output pjout 02h port pj direction pjdir 04h port pj pullup or pulldown enable pjren 06h port pj drive strength pjds 08h copyright ? 2009 ? 2015, texas instruments incorporated detailed description 71 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-31. ta0 registers (base address: 0340h) register description register offset ta0 control ta0ctl 00h capture/compare control 0 ta0cctl0 02h capture/compare control 1 ta0cctl1 04h capture/compare control 2 ta0cctl2 06h capture/compare control 3 ta0cctl3 08h capture/compare control 4 ta0cctl4 0ah ta0 counter register ta0r 10h capture/compare register 0 ta0ccr0 12h capture/compare register 1 ta0ccr1 14h capture/compare register 2 ta0ccr2 16h capture/compare register 3 ta0ccr3 18h capture/compare register 4 ta0ccr4 1ah ta0 expansion register 0 ta0ex0 20h ta0 interrupt vector ta0iv 2eh table 6-32. ta1 registers (base address: 0380h) register description register offset ta1 control ta1ctl 00h capture/compare control 0 ta1cctl0 02h capture/compare control 1 ta1cctl1 04h capture/compare control 2 ta1cctl2 06h ta1 counter register ta1r 10h capture/compare register 0 ta1ccr0 12h capture/compare register 1 ta1ccr1 14h capture/compare register 2 ta1ccr2 16h ta1 expansion register 0 ta1ex0 20h ta1 interrupt vector ta1iv 2eh 72 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-33. tb0 registers (base address: 03c0h) register description register offset tb0 control tb0ctl 00h capture/compare control 0 tb0cctl0 02h capture/compare control 1 tb0cctl1 04h capture/compare control 2 tb0cctl2 06h capture/compare control 3 tb0cctl3 08h capture/compare control 4 tb0cctl4 0ah capture/compare control 5 tb0cctl5 0ch capture/compare control 6 tb0cctl6 0eh tb0 register tb0r 10h capture/compare register 0 tb0ccr0 12h capture/compare register 1 tb0ccr1 14h capture/compare register 2 tb0ccr2 16h capture/compare register 3 tb0ccr3 18h capture/compare register 4 tb0ccr4 1ah capture/compare register 5 tb0ccr5 1ch capture/compare register 6 tb0ccr6 1eh tb0 expansion register 0 tb0ex0 20h tb0 interrupt vector tb0iv 2eh table 6-34. ta2 registers (base address: 0400h) register description register offset ta2 control ta2ctl 00h capture/compare control 0 ta2cctl0 02h capture/compare control 1 ta2cctl1 04h capture/compare control 2 ta2cctl2 06h ta2 counter register ta2r 10h capture/compare register 0 ta2ccr0 12h capture/compare register 1 ta2ccr1 14h capture/compare register 2 ta2ccr2 16h ta2 expansion register 0 ta2ex0 20h ta2 interrupt vector ta2iv 2eh copyright ? 2009 ? 2015, texas instruments incorporated detailed description 73 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-35. real-time clock registers (base address: 04a0h) register description register offset rtc control 0 rtcctl0 00h rtc control 1 rtcctl1 01h rtc control 2 rtcctl2 02h rtc control 3 rtcctl3 03h rtc prescaler 0 control rtcps0ctl 08h rtc prescaler 1 control rtcps1ctl 0ah rtc prescaler 0 rtcps0 0ch rtc prescaler 1 rtcps1 0dh rtc interrupt vector word rtciv 0eh rtc seconds, rtc counter register 1 rtcsec, rtcnt1 10h rtc minutes, rtc counter register 2 rtcmin, rtcnt2 11h rtc hours, rtc counter register 3 rtchour, rtcnt3 12h rtc day of week, rtc counter register 4 rtcdow, rtcnt4 13h rtc days rtcday 14h rtc month rtcmon 15h rtc year low rtcyearl 16h rtc year high rtcyearh 17h rtc alarm minutes rtcamin 18h rtc alarm hours rtcahour 19h rtc alarm day of week rtcadow 1ah rtc alarm days rtcaday 1bh 74 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-36. 32-bit hardware multiplier registers (base address: 04c0h) register description register offset 16-bit operand 1 ? multiply mpy 00h 16-bit operand 1 ? signed multiply mpys 02h 16-bit operand 1 ? multiply accumulate mac 04h 16-bit operand 1 ? signed multiply accumulate macs 06h 16-bit operand 2 op2 08h 16 16 result low word reslo 0ah 16 16 result high word reshi 0ch 16 16 sum extension register sumext 0eh 32-bit operand 1 ? multiply low word mpy32l 10h 32-bit operand 1 ? multiply high word mpy32h 12h 32-bit operand 1 ? signed multiply low word mpys32l 14h 32-bit operand 1 ? signed multiply high word mpys32h 16h 32-bit operand 1 ? multiply accumulate low word mac32l 18h 32-bit operand 1 ? multiply accumulate high word mac32h 1ah 32-bit operand 1 ? signed multiply accumulate low word macs32l 1ch 32-bit operand 1 ? signed multiply accumulate high word macs32h 1eh 32-bit operand 2 ? low word op2l 20h 32-bit operand 2 ? high word op2h 22h 32 32 result 0 ? least significant word res0 24h 32 32 result 1 res1 26h 32 32 result 2 res2 28h 32 32 result 3 ? most significant word res3 2ah mpy32 control register 0 mpy32ctl0 2ch copyright ? 2009 ? 2015, texas instruments incorporated detailed description 75 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-37. dma registers (base address dma general control: 0500h, dma channel 0: 0510h, dma channel 1: 0520h, dma channel 2: 0530h) register description register offset dma channel 0 control dma0ctl 00h dma channel 0 source address low dma0sal 02h dma channel 0 source address high dma0sah 04h dma channel 0 destination address low dma0dal 06h dma channel 0 destination address high dma0dah 08h dma channel 0 transfer size dma0sz 0ah dma channel 1 control dma1ctl 00h dma channel 1 source address low dma1sal 02h dma channel 1 source address high dma1sah 04h dma channel 1 destination address low dma1dal 06h dma channel 1 destination address high dma1dah 08h dma channel 1 transfer size dma1sz 0ah dma channel 2 control dma2ctl 00h dma channel 2 source address low dma2sal 02h dma channel 2 source address high dma2sah 04h dma channel 2 destination address low dma2dal 06h dma channel 2 destination address high dma2dah 08h dma channel 2 transfer size dma2sz 0ah dma module control 0 dmactl0 00h dma module control 1 dmactl1 02h dma module control 2 dmactl2 04h dma module control 3 dmactl3 06h dma module control 4 dmactl4 08h dma interrupt vector dmaiv 0eh table 6-38. usci_a0 registers (base address: 05c0h) register description register offset usci control 1 uca0ctl1 00h usci control 0 uca0ctl0 01h usci baud rate 0 uca0br0 06h usci baud rate 1 uca0br1 07h usci modulation control uca0mctl 08h usci status uca0stat 0ah usci receive buffer uca0rxbuf 0ch usci transmit buffer uca0txbuf 0eh usci lin control uca0abctl 10h usci irda transmit control uca0irtctl 12h usci irda receive control uca0irrctl 13h usci interrupt enable uca0ie 1ch usci interrupt flags uca0ifg 1dh usci interrupt vector word uca0iv 1eh 76 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-39. usci_b0 registers (base address: 05e0h) register description register offset usci synchronous control 1 ucb0ctl1 00h usci synchronous control 0 ucb0ctl0 01h usci synchronous bit rate 0 ucb0br0 06h usci synchronous bit rate 1 ucb0br1 07h usci synchronous status ucb0stat 0ah usci synchronous receive buffer ucb0rxbuf 0ch usci synchronous transmit buffer ucb0txbuf 0eh usci i2c own address ucb0i2coa 10h usci i2c slave address ucb0i2csa 12h usci interrupt enable ucb0ie 1ch usci interrupt flags ucb0ifg 1dh usci interrupt vector word ucb0iv 1eh table 6-40. usci_a1 registers (base address: 0600h) register description register offset usci control 1 uca1ctl1 00h usci control 0 uca1ctl0 01h usci baud rate 0 uca1br0 06h usci baud rate 1 uca1br1 07h usci modulation control uca1mctl 08h usci status uca1stat 0ah usci receive buffer uca1rxbuf 0ch usci transmit buffer uca1txbuf 0eh usci lin control uca1abctl 10h usci irda transmit control uca1irtctl 12h usci irda receive control uca1irrctl 13h usci interrupt enable uca1ie 1ch usci interrupt flags uca1ifg 1dh usci interrupt vector word uca1iv 1eh copyright ? 2009 ? 2015, texas instruments incorporated detailed description 77 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-41. usci_b1 registers (base address: 0620h) register description register offset usci synchronous control 1 ucb1ctl1 00h usci synchronous control 0 ucb1ctl0 01h usci synchronous bit rate 0 ucb1br0 06h usci synchronous bit rate 1 ucb1br1 07h usci synchronous status ucb1stat 0ah usci synchronous receive buffer ucb1rxbuf 0ch usci synchronous transmit buffer ucb1txbuf 0eh usci i2c own address ucb1i2coa 10h usci i2c slave address ucb1i2csa 12h usci interrupt enable ucb1ie 1ch usci interrupt flags ucb1ifg 1dh usci interrupt vector word ucb1iv 1eh 78 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-42. adc12_a registers (base address: 0700h) register description register offset control register 0 adc12ctl0 00h control register 1 adc12ctl1 02h control register 2 adc12ctl2 04h interrupt-flag register adc12ifg 0ah interrupt-enable register adc12ie 0ch interrupt-vector-word register adc12iv 0eh adc memory-control register 0 adc12mctl0 10h adc memory-control register 1 adc12mctl1 11h adc memory-control register 2 adc12mctl2 12h adc memory-control register 3 adc12mctl3 13h adc memory-control register 4 adc12mctl4 14h adc memory-control register 5 adc12mctl5 15h adc memory-control register 6 adc12mctl6 16h adc memory-control register 7 adc12mctl7 17h adc memory-control register 8 adc12mctl8 18h adc memory-control register 9 adc12mctl9 19h adc memory-control register 10 adc12mctl10 1ah adc memory-control register 11 adc12mctl11 1bh adc memory-control register 12 adc12mctl12 1ch adc memory-control register 13 adc12mctl13 1dh adc memory-control register 14 adc12mctl14 1eh adc memory-control register 15 adc12mctl15 1fh conversion memory 0 adc12mem0 20h conversion memory 1 adc12mem1 22h conversion memory 2 adc12mem2 24h conversion memory 3 adc12mem3 26h conversion memory 4 adc12mem4 28h conversion memory 5 adc12mem5 2ah conversion memory 6 adc12mem6 2ch conversion memory 7 adc12mem7 2eh conversion memory 8 adc12mem8 30h conversion memory 9 adc12mem9 32h conversion memory 10 adc12mem10 34h conversion memory 11 adc12mem11 36h conversion memory 12 adc12mem12 38h conversion memory 13 adc12mem13 3ah conversion memory 14 adc12mem14 3ch conversion memory 15 adc12mem15 3eh copyright ? 2009 ? 2015, texas instruments incorporated detailed description 79 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-43. comparator_b registers (base address: 08c0h) register description register offset comp_b control register 0 cbctl0 00h comp_b control register 1 cbctl1 02h comp_b control register 2 cbctl2 04h comp_b control register 3 cbctl3 06h comp_b interrupt register cbint 0ch comp_b interrupt vector word cbiv 0eh table 6-44. usb configuration registers (base address: 0900h) register description register offset usb key and id usbkeyid 00h usb module configuration usbcnf 02h usb phy control usbphyctl 04h usb power control usbpwrctl 08h usb pll control usbpllctl 10h usb pll divider usbplldiv 12h usb pll interrupts usbpllir 14h table 6-45. usb control registers (base address: 0920h) register description register offset input endpoint_0 configuration usbiepcnf_0 00h input endpoint_0 byte count usbiepcnt_0 01h output endpoint_0 configuration usboepcnf_0 02h output endpoint_0 byte count usboepcnt_0 03h input endpoint interrupt enables usbiepie 0eh output endpoint interrupt enables usboepie 0fh input endpoint interrupt flags usbiepifg 10h output endpoint interrupt flags usboepifg 11h usb interrupt vector usbiv 12h usb maintenance usbmaint 16h timestamp usbtsreg 18h usb frame number usbfn 1ah usb control usbctl 1ch usb interrupt enables usbie 1dh usb interrupt flags usbifg 1eh function address usbfunadr 1fh 80 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10 input/output schematics 6.10.1 port p1, p1.0 to p1.7, input/output with schmitt trigger copyright ? 2009 ? 2015, texas instruments incorporated detailed description 81 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p1.0/ta0clk/aclk p1.1/ta0.0 p1.2/ta0.1 p1.3/ta0.2 p1.4/ta0.3 p1.5/ta0.4 p1.6/ta1clk/cbout p1.7/ta1.0 direction0: input 1: output p1sel.x 1 0 p1dir.x p1in.x p1irq.x en to module 1 0 from module p1out.x interrupt edge select q en set p1sel.x p1ies.x p1ifg.x p1ie.x 1 0 dv ss dv cc p1ren.x pad logic 1 p1ds.x0: low drive 1: high drive d from module
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-46. port p1 (p1.0 to p1.7) pin functions control bits or signals pin name (p1.x) x function p1dir.x p1sel.x p1.0/ta0clk/aclk 0 p1.0 (i/o) i: 0; o: 1 0 ta0clk 0 1 aclk 1 1 p1.1/ta0.0 1 p1.1 (i/o) i: 0; o: 1 0 ta0.cci0a 0 1 ta0.0 1 1 p1.2/ta0.1 2 p1.2 (i/o) i: 0; o: 1 0 ta0.cci1a 0 1 ta0.1 1 1 p1.3/ta0.2 3 p1.3 (i/o) i: 0; o: 1 0 ta0.cci2a 0 1 ta0.2 1 1 p1.4/ta0.3 4 p1.4 (i/o) i: 0; o: 1 0 ta0.cci3a 0 1 ta0.3 1 1 p1.5/ta0.4 5 p1.5 (i/o) i: 0; o: 1 0 ta0.cci4a 0 1 ta0.4 1 1 p1.6/ta1clk/cbout 6 p1.6 (i/o) i: 0; o: 1 0 ta1clk 0 1 cbout comparator b 1 1 p1.7/ta1.0 7 p1.7 (i/o) i: 0; o: 1 0 ta1.cci0a 0 1 ta1.0 1 1 82 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.2 port p2, p2.0 to p2.7, input/output with schmitt trigger copyright ? 2009 ? 2015, texas instruments incorporated detailed description 83 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p2.0/ta1.1 p2.1/ta1.2 p2.2/ta2clk/smclk p2.3/ta2.0 p2.4/ta2.1 p2.5/ta2.2 p2.6/rtcclk/dmae0 p2.7/ub0ste/uca0clk direction0: input 1: output p2sel.x 1 0 p2dir.x p2in.x to module en to module 1 0 from module p2out.x interrupt edge select q en set p2sel.x p2ies.x p2ifg.x p2ie.x 1 0 dv ss dv cc p2ren.x pad logic 1 p2ds.x0: low drive 1: high drive d from module
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-47. port p2 (p2.0 to p2.7) pin functions control bits or signals (1) pin name (p2.x) x function p2dir.x p2sel.x p2.0/ta1.1 0 p2.0 (i/o) i: 0; o: 1 0 ta1.cci1a 0 1 ta1.1 1 1 p2.1/ta1.2 1 p2.1 (i/o) i: 0; o: 1 0 ta1.cci2a 0 1 ta1.2 1 1 p2.2/ta2clk/smclk 2 p2.2 (i/o) i: 0; o: 1 0 ta2clk 0 1 smclk 1 1 p2.3/ta2.0 3 p2.3 (i/o) i: 0; o: 1 0 ta2.cci0a 0 1 ta2.0 1 1 p2.4/ta2.1 4 p2.4 (i/o) i: 0; o: 1 0 ta2.cci1a 0 1 ta2.1 1 1 p2.5/ta2.2 5 p2.5 (i/o) i: 0; o: 1 0 ta2.cci2a 0 1 ta2.2 1 1 p2.6/rtcclk/dmae0 6 p2.6 (i/o) i: 0; o: 1 0 dmae0 0 1 rtcclk 1 1 p2.7/ucb0ste/uca0clk 7 p2.7 (i/o) i: 0; o: 1 0 ucb0ste/uca0clk (2) (3) x 1 (1) x = don ' t care (2) the pin direction is controlled by the usci module. (3) uca0clk function takes precedence over ucb0ste function. if the pin is required as uca0clk input or output, usci b0 is forced to 3-wire spi mode if 4-wire spi mode is selected. 84 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.3 port p3, p3.0 to p3.7, input/output with schmitt trigger table 6-48. port p3 (p3.0 to p3.7) pin functions control bits or signals (1) pin name (p3.x) x function p3dir.x p3sel.x p3.0/ucb0simo/ucb0sda 0 p3.0 (i/o) i: 0; o: 1 0 ucb0simo/ucb0sda (2) (3) x 1 p3.1/ucb0somi/ucb0scl 1 p3.1 (i/o) i: 0; o: 1 0 ucb0somi/ucb0scl (2) (3) x 1 p3.2/ucb0clk/uca0ste 2 p3.2 (i/o) i: 0; o: 1 0 ucb0clk/uca0ste (2) (4) x 1 p3.3/uca0txd/uca0simo 3 p3.3 (i/o) i: 0; o: 1 0 uca0txd/uca0simo (2) x 1 p3.4/uca0rxd/uca0somi 4 p3.4 (i/o) i: 0; o: 1 0 uca0rxd/uca0somi (2) x 1 p3.5/tb0.5 (5) 5 p3.5 (i/o) i: 0; o: 1 0 tb0.cci5a 0 1 tb0.5 1 1 p3.6/tb0.6 (5) 6 p3.6 (i/o) i: 0; o: 1 0 tb0.cci6a 0 1 tb0.6 1 1 p3.7/tb0outh/svmout (5) 7 p3.7 (i/o) i: 0; o: 1 0 tb0outh 0 1 svmout 1 1 (1) x = don ' t care (2) the pin direction is controlled by the usci module. (3) if the i 2 c functionality is selected, the output drives only the logical 0 to v ss level. (4) ucb0clk function takes precedence over uca0ste function. if the pin is required as ucb0clk input or output, usci a0 is forced to 3-wire spi mode if 4-wire spi mode is selected. (5) f5529, f5527, f5525, f5521, f5519, f5517, f5515 devices only. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 85 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p3.0/ucb0simo/ucb0sdap3.1/ucb0somi/ucb0scl p3.2/ucb0clk/uca0ste p3.3/uca0txd/uca0simo p3.4/uca0rxd/uca0somi p3.5/tb0.5 p3.6/tb0.6 p3.7/tb0outh/svmout direction0: input 1: output p3sel.x 1 0 p3dir.x p3in.x en to module 1 0 from module p3out.x 1 0 dv ss dv cc p3ren.x pad logic 1 p3ds.x0: low drive 1: high drive d from module
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.10.4 port p4, p4.0 to p4.7, input/output with schmitt trigger table 6-49. port p4 (p4.0 to p4.7) pin functions control bits or signals pin name (p4.x) x function p4dir.x (1) p4sel.x p4mapx p4.0/p4map0 0 p4.0 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.1/p4map1 1 p4.1 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.2/p4map2 2 p4.2 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.3/p4map3 3 p4.3 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.4/p4map4 4 p4.4 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.5/p4map5 5 p4.5 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.6/p4map6 6 p4.6 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 p4.7/p4map7 7 p4.7 (i/o) i: 0; o: 1 0 x mapped secondary digital function x 1 30 (1) the direction of some mapped secondary functions are controlled directly by the module. see table 6-7 for specific direction control information of mapped secondary functions. 86 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p4.0/p4map0p4.1/p4map1 p4.2/p4map2 p4.3/p4map3 p4.4/p4map4 p4.5/p4map5 p4.6/p4map6 p4.7/p4map7 direction0: input 1: output p4sel.x 1 0 p4dir.x p4in.x en to port mapping control 1 0 from port mapping control p4out.x 1 0 dv ss dv cc p4ren.x pad logic 1 p4ds.x0: low drive 1: high drive d from port mapping control
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.5 port p5, p5.0 and p5.1, input/output with schmitt trigger table 6-50. port p5 (p5.0 and p5.1) pin functions control bits or signals (1) pin name (p5.x) x function p5dir.x p5sel.x refout p5.0/a8/vref+/veref+ (2) 0 p5.0 (i/o) (3) i: 0; o: 1 0 x a8/veref+ (4) x 1 0 a8/vref+ (5) x 1 1 p5.1/a9/vref-/veref- (6) 1 p5.1 (i/o) (3) i: 0; o: 1 0 x a9/veref ? (7) x 1 0 a9/vref ? (8) x 1 1 (1) x = don ' t care (2) vref+/veref+ available on msp430f552x devices only. (3) default condition (4) setting the p5sel.0 bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. an external voltage can be applied to veref+ and used as the reference for the adc12_a when available. channel a8, when selected with the inchx bits, is connected to the vref+/veref+ pin. (5) setting the p5sel.0 bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. the vref+ reference is available at the pin. channel a8, when selected with the inchx bits, is connected to the vref+/veref+ pin. (6) vref-/veref- available on msp430f552x devices only. (7) setting the p5sel.1 bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. an external voltage can be applied to veref- and used as the reference for the adc12_a when available. channel a9, when selected with the inchx bits, is connected to the vref-/veref- pin. (8) setting the p5sel.1 bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. the vref ? reference is available at the pin. channel a9, when selected with the inchx bits, is connected to the vref- /veref- pin. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 87 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.0/(a8/vref+/veref+) p5.1/(a9/vrefC/verefC) p5sel.x 1 0 p5dir.x p5in.x en to module 1 0 from module p5out.x 1 0 dv ss dv cc p5ren.x pad logic 1 p5ds.x0: low drive 1: high drive d bus keeper to/from reference (n/a msp430f551x) to adc12 inchx = x (n/a mspf430f551x) (n/a mspf430f551x)
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.10.6 port p5, p5.2, input/output with schmitt trigger 88 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.2/xt2in p5sel.2 1 0 p5dir.2 p5in.2 en module x in 1 0 module x out p5out.2 1 0 dv ss dv cc p5ren.2 pad logic 1 p5ds.20: low drive 1: high drive d bus keeper to xt2
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.7 port p5, p5.3, input/output with schmitt trigger table 6-51. port p5 (p5.2, p5.3) pin functions control bits or signals (1) pin name (p5.x) x function p5dir.x p5sel.2 p5sel.3 xt2bypass p5.2/xt2in 2 p5.2 (i/o) i: 0; o: 1 0 x x xt2in crystal mode (2) x 1 x 0 xt2in bypass mode (2) x 1 x 1 p5.3/xt2out 3 p5.3 (i/o) i: 0; o: 1 0 0 x xt2out crystal mode (3) x 1 x 0 p5.3 (i/o) (3) x 1 0 1 (1) x = don ' t care (2) setting p5sel.2 causes the general-purpose i/o to be disabled. pending the setting of xt2bypass, p5.2 is configured for crystal mode or bypass mode. (3) setting p5sel.2 causes the general-purpose i/o to be disabled in crystal mode. when using bypass mode, p5.3 can be used as general-purpose i/o. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 89 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.3/xt2out 1 0 p5dir.3 p5in.3 en module x in 1 0 module x out p5out.3 1 0 dv ss dv cc p5ren.3 pad logic 1 p5ds.30: low drive 1: high drive d bus keeper to xt2 p5sel.2 xt2bypass p5sel.3
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.10.7.1 port p5, p5.4 and p5.5 input/output with schmitt trigger 90 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.4/xin p5sel.4 1 0 p5dir.4 p5in.4 en module x in 1 0 module x out p5out.4 1 0 dv ss dv cc p5ren.4 pad logic 1 p5ds.40: low drive 1: high drive d bus keeper to xt1
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-52. port p5 (p5.4 and p5.5) pin functions control bits or signals (1) pin name (p5.x) x function p5dir.x p5sel.4 p5sel.5 xt1bypass p5.4/xin 4 p5.4 (i/o) i: 0; o: 1 0 x x xin crystal mode (2) x 1 x 0 xin bypass mode (2) x 1 x 1 p5.5/xout 5 p5.5 (i/o) i: 0; o: 1 0 0 x xout crystal mode (3) x 1 x 0 p5.5 (i/o) (3) x 1 0 1 (1) x = don ' t care (2) setting p5sel.4 causes the general-purpose i/o to be disabled. pending the setting of xt1bypass, p5.4 is configured for crystal mode or bypass mode. (3) setting p5sel.4 causes the general-purpose i/o to be disabled in crystal mode. when using bypass mode, p5.5 can be used as general-purpose i/o. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 91 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.5/xout 1 0 p5dir.5 p5in.5 en module x in 1 0 module x out p5out.5 1 0 dv ss dv cc p5ren.5 pad logic 1 p5ds.50: low drive 1: high drive d bus keeper to xt1 p5sel.4 xt1bypass p5sel.5
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.10.8 port p5, p5.6 to p5.7, input/output with schmitt trigger table 6-53. port p5 (p5.6 to p5.7) pin functions control bits or signals pin name (p5.x) x function p5dir.x p5sel.x p5.6/tb0.0 (1) 6 p5.6 (i/o) i: 0; o: 1 0 tb0.cci0a 0 1 tb0.0 1 1 p5.7/tb0.1 (1) 7 tb0.cci1a 0 1 tb0.1 1 1 (1) f5529, f5527, f5525, f5521, f5519, f5517, f5515 devices only. 92 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p5.6/tb0.0p5.7/tb0.1 direction0: input 1: output p5sel.x 1 0 p5dir.x p5in.x en to module 1 0 from module p5out.x 1 0 dv ss dv cc p5ren.x pad logic 1 p5ds.x0: low drive 1: high drive d
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.9 port p6, p6.0 to p6.7, input/output with schmitt trigger copyright ? 2009 ? 2015, texas instruments incorporated detailed description 93 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p6.0/cb0/(a0)p6.1/cb1/(a1) p6.2/cb2/(a2) p6.3/cb3/(a3) p6.4/cb4/(a4) p6.5/cb5/(a5) p6.6/cb6/(a6) p6.7/cb7/(a7) p6sel.x 1 0 p6dir.x p6in.x en to module 1 0 from module p6out.x 1 0 dvssdvcc 1 p6ds.x0: low drive 1: high drive d to comparator_b from comparator_b pad logic to adc12 inchx = x (n/a mspf430f551x) bus keeper direction0: input 1: output cbpd.x p6ren.x (n/a mspf430f551x)
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-54. port p6 (p6.0 to p6.7) pin functions control bits or signals pin name (p6.x) x function p6dir.x p6sel.x cbpd p6.0/cb0/(a0) 0 p6.0 (i/o) i: 0; o: 1 0 0 a0 (only msp430f552x) x 1 x cb0 (1) x x 1 p6.1/cb1/(a1) 1 p6.1 (i/o) i: 0; o: 1 0 0 a1 (only msp430f552x) x 1 x cb1 (1) x x 1 p6.2/cb2/(a2) 2 p6.2 (i/o) i: 0; o: 1 0 0 a2 (only msp430f552x) x 1 x cb2 (1) x x 1 p6.3/cb3/(a3) 3 p6.3 (i/o) i: 0; o: 1 0 0 a3 (only msp430f552x) x 1 x cb3 (1) x x 1 p6.4/cb4/(a4) 4 p6.4 (i/o) i: 0; o: 1 0 0 a4 (only msp430f552x) x 1 x cb4 (1) x x 1 p6.5/cb5/(a5) 5 p6.5 (i/o) i: 0; o: 1 0 0 a5 (only msp430f552x) x 1 x cb5 (1) x x 1 p6.6/cb6/(a6) 6 p6.6 (i/o) i: 0; o: 1 0 0 a6 (only msp430f552x) x 1 x cb6 (1) x x 1 p6.7/cb7/(a7) 7 p6.7 (i/o) i: 0; o: 1 0 0 a7 (only msp430f552x) x 1 x cb7 (1) x x 1 (1) setting the cbpd.x bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cbx input pin to the comparator multiplexer with the cbx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated cbpd.x bit. 94 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.10 port p7, p7.0 to p7.3, input/output with schmitt trigger copyright ? 2009 ? 2015, texas instruments incorporated detailed description 95 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p7.0/cb8/(a12)p7.1/cb9/(a13) p7.2/cb10/(a14) p7.3/cb11/(a15) p7sel.x 1 0 p7dir.x p7in.x en to module 1 0 from module p7out.x 1 0 dvssdvcc 1 p7ds.x0: low drive 1: high drive d to comparator_b from comparator_b pad logic to adc12 (n/a mspf430f551x) inchx = x (n/a mspf430f551x) bus keeper direction0: input 1: output cbpd.x p7ren.x
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-55. port p7 (p7.0 to p7.3) pin functions control bits or signals pin name (p7.x) x function p7dir.x p7sel.x cbpd p7.0/cb8/(a12) 0 p7.0 (i/o) (1) i: 0; o: 1 0 0 a12 (2) x 1 x cb8 (3) (1) x x 1 p7.1/cb9/(a13) 1 p7.1 (i/o) (1) i: 0; o: 1 0 0 a13 (2) x 1 x cb9 (3) (1) x x 1 p7.2/cb10/(a14) 2 p7.2 (i/o) (1) i: 0; o: 1 0 0 a14 (2) x 1 x cb10 (3) (1) x x 1 p7.3/cb11/(a15) 3 p7.3 (i/o) (1) i: 0; o: 1 0 0 a15 (2) x 1 x cb11 (3) (1) x x 1 (1) f5529, f5527, f5525, f5521, f5519, f5517, f5515 devices only (2) f5529, f5527, f5525, f5521 devices only (3) setting the cbpd.x bit disables the output driver and the input schmitt trigger to prevent parasitic cross currents when applying analog signals. selecting the cbx input pin to the comparator multiplexer with the cbx bits automatically disables output driver and input buffer for that pin, regardless of the state of the associated cbpd.x bit. 96 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.11 port p7, p7.4 to p7.7, input/output with schmitt trigger table 6-56. port p7 (p7.4 to p7.7) pin functions control bits or signals pin name (p7.x) x function p7dir.x p7sel.x p7.4/tb0.2 (1) 4 p7.4 (i/o) i: 0; o: 1 0 tb0.cci2a 0 1 tb0.2 1 1 p7.5/tb0.3 (1) 5 p7.5 (i/o) i: 0; o: 1 0 tb0.cci3a 0 1 tb0.3 1 1 p7.6/tb0.4 (1) 6 p7.6 (i/o) i: 0; o: 1 0 tb0.cci4a 0 1 tb0.4 1 1 p7.7/tb0clk/mclk (1) 7 p7.7 (i/o) i: 0; o: 1 0 tb0clk 0 1 mclk 1 1 (1) f5529, f5527, f5525, f5521, f5519, f5517, f5515 devices only copyright ? 2009 ? 2015, texas instruments incorporated detailed description 97 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p7.4/tb0.2p7.5/tb0.3 p7.6/tb0.4 p7.7/tb0clk/mclk direction0: input 1: output p7sel.x 1 0 p7dir.x p7in.x en to module 1 0 from module p7out.x 1 0 dv ss dv cc p7ren.x pad logic 1 p7ds.x0: low drive 1: high drive d
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 6.10.12 port p8, p8.0 to p8.2, input/output with schmitt trigger table 6-57. port p8 (p8.0 to p8.2) pin functions control bits or signals pin name (p8.x) x function p8dir.x p8sel.x p8.0 (1) 0 p8.0(i/o) i: 0; o: 1 0 p8.1 (1) 1 p8.1(i/o) i: 0; o: 1 0 p8.2 (1) 2 p8.2(i/o) i: 0; o: 1 0 (1) f5529, f5527, f5525, f5521, f5519, f5517, f5515 devices only 98 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 p8.0p8.1 p8.2 direction0: input 1: output p8sel.x 1 0 p8dir.x p8in.x en to port mapping control 1 0 from port mapping control p8out.x 1 0 dv ss dv cc p8ren.x pad logic 1 p8ds.x0: low drive 1: high drive d from port mapping control
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.13 port pu.0/dp, pu.1/dm, pur usb ports copyright ? 2009 ? 2015, texas instruments incorporated detailed description 99 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 puope 01 01 puout0 pusel pad logic pu.0 / dp vusb vssu pu.1/ dm 01 puout 1 . puin1 usb dm input puin0 usb dp input usb dm output usb dp output usb output enable pusel pad logic pur vusb vssu 1 puren purin puipe
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-58. port pu.0/dp, pu.1/dm output functions (1) control bits pin name pusel puope puout1 puout0 pu.1/dm pu.0/dp 0 0 x x output disabled output disabled 0 1 0 0 output low output low 0 1 0 1 output low output high 0 1 1 0 output high output low 0 1 1 1 output high output high 1 x x x dm (2) dp (2) (1) pu.1/dm and pu.0/dp inputs and outputs are supplied from vusb. vusb can be generated by the device using the integrated 3.3-v ldo when enabled. vusb can also be supplied externally when the 3.3-v ldo is not being used and is disabled. (2) output state set by the usb module. table 6-59. port pu.0/dp, pu.1/dm input functions (1) control bits pin name pusel puipe pu.1/dm pu.0/dp 0 0 input disabled input disabled 0 1 input enabled input enabled 1 x dm input dp input (1) pu.1/dm and pu.0/dp inputs and outputs are supplied from vusb. vusb can be generated by the device using the integrated 3.3-v ldo when enabled. vusb can also be supplied externally when the 3.3-v ldo is not being used and is disabled. table 6-60. port pur input functions control bits function pusel puren input disabled 0 0 pullup disabled input disabled 0 1 pullup enabled input enabled 1 0 pullup disabled input enabled 1 1 pullup enabled 100 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.10.14 port j, j.0 jtag pin tdo, input/output with schmitt trigger or output 6.10.15 port j, j.1 to j.3 jtag pins tms, tck, tdi/tclk, input/output with schmitt trigger or output copyright ? 2009 ? 2015, texas instruments incorporated detailed description 101 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 pj.1/tdi/tclkpj.2/tms pj.3/tck from jtag 1 0 pjdir.x pjin.x en 1 0 from jtag pjout.x 1 0 dv ss dv cc pjren.x pad logic 1 pjds.x0: low drive 1: high drive d dvss to jtag pj.0/tdo from jtag 1 0 pjdir.0 pjin.0 en 1 0 from jtag pjout.0 1 0 dv ss dv cc pjren.0 pad logic 1 pjds.00: low drive 1: high drive d dvcc
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-61. port pj (pj.0 to pj.3) pin functions control bits/ signals (1) pin name (pj.x) x function pjdir.x pj.0/tdo 0 pj.0 (i/o) (2) i: 0; o: 1 tdo (3) x pj.1/tdi/tclk 1 pj.1 (i/o) (2) i: 0; o: 1 tdi/tclk (3) (4) x pj.2/tms 2 pj.2 (i/o) (2) i: 0; o: 1 tms (3) (4) x pj.3/tck 3 pj.3 (i/o) (2) i: 0; o: 1 tck (3) (4) x (1) x = don ' t care (2) default condition (3) the pin direction is controlled by the jtag module. (4) in jtag mode, pullups are activated automatically on tms, tck, and tdi/tclk. pjren.x are do not care. 102 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 6.11 device descriptors (tlv) table 6-62 and table 6-63 list the complete contents of the device descriptor tag-length-value (tlv) structure for each device type. table 6-62. msp430f552x device descriptor table (1) value size description address (bytes) f5529 f5528 f5527 f5526 f5525 f5524 f5522 f5521 info block info length 01a00h 1 06h 06h 06h 06h 06h 06h 06h 06h crc length 01a01h 1 06h 06h 06h 06h 06h 06h 06h 06h crc value 01a02h 2 per unit per unit per unit per unit per unit per unit per unit per unit device id 01a04h 1 55h 55h 55h 55h 55h 55h 55h 55h device id 01a05h 1 29h 28h 27h 26h 25h 24h 22h 21h hardware revision 01a06h 1 per unit per unit per unit per unit per unit per unit per unit per unit firmware revision 01a07h 1 per unit per unit per unit per unit per unit per unit per unit per unit die record die record tag 01a08h 1 08h 08h 08h 08h 08h 08h 08h 08h die record length 01a09h 1 0ah 0ah 0ah 0ah 0ah 0ah 0ah 0ah lot/wafer id 01a0ah 4 per unit per unit per unit per unit per unit per unit per unit per unit die x position 01a0eh 2 per unit per unit per unit per unit per unit per unit per unit per unit die y position 01a10h 2 per unit per unit per unit per unit per unit per unit per unit per unit test results 01a12h 2 per unit per unit per unit per unit per unit per unit per unit per unit adc12 adc12 calibration tag 01a14h 1 11h 11h 11h 11h 11h 11h 11h 11h calibration adc12 calibration length 01a15h 1 10h 10h 10h 10h 10h 10h 10h 10h adc gain factor 01a16h 2 per unit per unit per unit per unit per unit per unit per unit per unit adc offset 01a18h 2 per unit per unit per unit per unit per unit per unit per unit per unit adc 1.5-v reference 01a1ah 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 30 c adc 1.5-v reference 01a1ch 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 85 c adc 2.0-v reference 01a1eh 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 30 c adc 2.0-v reference 01a20h 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 85 c adc 2.5-v reference 01a22h 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 30 c adc 2.5-v reference 01a24h 2 per unit per unit per unit per unit per unit per unit per unit per unit temp. sensor 85 c ref ref calibration tag 01a26h 1 12h 12h 12h 12h 12h 12h 12h 12h calibration ref calibration length 01a27h 1 06h 06h 06h 06h 06h 06h 06h 06h ref 1.5-v reference 01a28h 2 per unit per unit per unit per unit per unit per unit per unit per unit factor ref 2.0-v reference 01a2ah 2 per unit per unit per unit per unit per unit per unit per unit per unit factor ref 2.5-v reference 01a2ch 2 per unit per unit per unit per unit per unit per unit per unit per unit factor peripheral peripheral descriptor tag 01a2eh 1 02h 02h 02h 02h 02h 02h 02h 02h descriptor peripheral descriptor 01a2fh 1 63h 61h 65h 63h 63h 61h 61h 64h length 08h 08h 08h 08h 08h 08h 08h 08h memory 1 2 8ah 8ah 8ah 8ah 8ah 8ah 8ah 8ah 0ch 0ch 0ch 0ch 0ch 0ch 0ch 0ch memory 2 2 86h 86h 86h 86h 86h 86h 86h 86h 0eh 0eh 0eh 0eh 0eh 0eh 0eh 0eh memory 3 2 2ah 2ah 2ah 2ah 2ah 2ah 2ah 2ah 12h 12h 12h 12h 12h 12h 12h 12h memory 4 2 2eh 2eh 2dh 2dh 2ch 2ch 2eh 2dh 22h 22h 2ah 2ah 22h 22h 40h 2ah memory 5 2 96h 96h 22h 22h 94h 94h 92h 40h (1) na = not applicable, blank = unused and reads ffh. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 103 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-62. msp430f552x device descriptor table (1) (continued) value size description address (bytes) f5529 f5528 f5527 f5526 f5525 f5524 f5522 f5521 95h 95h memory 6 1/2 n/a n/a n/a n/a n/a 92h 92h 92h delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h peripheral count 1 21h 20h 21h 20h 21h 20h 20h 21h 00h 00h 00h 00h 00h 00h 00h 00h msp430cpuxv2 2 23h 23h 23h 23h 23h 23h 23h 23h 00h 00h 00h 00h 00h 00h 00h 00h jtag 2 09h 09h 09h 09h 09h 09h 09h 09h 00h 00h 00h 00h 00h 00h 00h 00h sbw 2 0fh 0fh 0fh 0fh 0fh 0fh 0fh 0fh 00h 00h 00h 00h 00h 00h 00h 00h eem-l 2 05h 05h 05h 05h 05h 05h 05h 05h 00h 00h 00h 00h 00h 00h 00h 00h ti bsl 2 fch fch fch fch fch fch fch fch 10h 10h 10h 10h 10h 10h 10h 10h sfr 2 41h 41h 41h 41h 41h 41h 41h 41h 02h 02h 02h 02h 02h 02h 02h 02h pmm 2 30h 30h 30h 30h 30h 30h 30h 30h 02h 02h 02h 02h 02h 02h 02h 02h fctl 2 38h 38h 38h 38h 38h 38h 38h 38h 01h 01h 01h 01h 01h 01h 01h 01h crc16 2 3ch 3ch 3ch 3ch 3ch 3ch 3ch 3ch 00h 00h 00h 00h 00h 00h 00h 00h crc16_rb 2 3dh 3dh 3dh 3dh 3dh 3dh 3dh 3dh 00h 00h 00h 00h 00h 00h 00h 00h ramctl 2 44h 44h 44h 44h 44h 44h 44h 44h 00h 00h 00h 00h 00h 00h 00h 00h wdt_a 2 40h 40h 40h 40h 40h 40h 40h 40h 01h 01h 01h 01h 01h 01h 01h 01h ucs 2 48h 48h 48h 48h 48h 48h 48h 48h 02h 02h 02h 02h 02h 02h 02h 02h sys 2 42h 42h 42h 42h 42h 42h 42h 42h 03h 03h 03h 03h 03h 03h 03h 03h ref 2 a0h a0h a0h a0h a0h a0h a0h a0h 01h 01h 01h 01h 01h 01h 01h 01h port mapping 2 10h 10h 10h 10h 10h 10h 10h 10h 04h 04h 04h 04h 04h 04h 04h 04h port 1/2 2 51h 51h 51h 51h 51h 51h 51h 51h 02h 02h 02h 02h 02h 02h 02h 02h port 3/4 2 52h 52h 52h 52h 52h 52h 52h 52h 02h 02h 02h 02h 02h 02h 02h 02h port 5/6 2 53h 53h 53h 53h 53h 53h 53h 53h 02h 02h 02h 02h port 7/8 2 n/a n/a n/a n/a 54h 54h 54h 54h 0ch 0eh 0ch 0eh 0ch 0eh 0eh 0ch jtag 2 5fh 5fh 5fh 5fh 5fh 5fh 5fh 5fh 02h 02h 02h 02h 02h 02h 02h 02h ta0 2 62h 62h 62h 62h 62h 62h 62h 62h 04h 04h 04h 04h 04h 04h 04h 04h ta1 2 61h 61h 61h 61h 61h 61h 61h 61h 04h 04h 04h 04h 04h 04h 04h 04h tb0 2 67h 67h 67h 67h 67h 67h 67h 67h 04h 04h 04h 04h 04h 04h 04h 04h ta2 2 61h 61h 61h 61h 61h 61h 61h 61h 0ah 0ah 0ah 0ah 0ah 0ah 0ah 0ah rtc 2 68h 68h 68h 68h 68h 68h 68h 68h 02h 02h 02h 02h 02h 02h 02h 02h mpy32 2 85h 85h 85h 85h 85h 85h 85h 85h 04h 04h 04h 04h 04h 04h 04h 04h dma-3 2 47h 47h 47h 47h 47h 47h 47h 47h 104 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-62. msp430f552x device descriptor table (1) (continued) value size description address (bytes) f5529 f5528 f5527 f5526 f5525 f5524 f5522 f5521 0ch 0ch 0ch 0ch 0ch 0ch 0ch 0ch usci_a/b 2 90h 90h 90h 90h 90h 90h 90h 90h 04h 04h 04h 04h 04h 04h 04h 04h usci_a/b 2 90h 90h 90h 90h 90h 90h 90h 90h 10h 10h 10h 10h 10h 10h 10h 10h adc12_a 2 d1h d1h d1h d1h d1h d1h d1h d1h 1ch 1ch 1ch 1ch 1ch 1ch 1ch 1ch comp_b 2 a8h a8h a8h a8h a8h a8h a8h a8h 04h 04h 04h 04h 04h 04h 04h 04h usb 2 98h 98h 98h 98h 98h 98h 98h 98h interrupts comp_b 1 a8h a8h a8h a8h a8h a8h a8h a8h tb0.ccifg0 1 64h 64h 64h 64h 64h 64h 64h 64h tb0.ccifg1..6 1 65h 65h 65h 65h 65h 65h 65h 65h wdtifg 1 40h 40h 40h 40h 40h 40h 40h 40h usci_a0 1 90h 90h 90h 90h 90h 90h 90h 90h usci_b0 1 91h 91h 91h 91h 91h 91h 91h 91h adc12_a 1 d0h d0h d0h d0h d0h d0h d0h d0h ta0.ccifg0 1 60h 60h 60h 60h 60h 60h 60h 60h ta0.ccifg1..4 1 61h 61h 61h 61h 61h 61h 61h 61h usb 1 98h 98h 98h 98h 98h 98h 98h 98h dma 1 46h 46h 46h 46h 46h 46h 46h 46h ta1.ccifg0 1 62h 62h 62h 62h 62h 62h 62h 62h ta1.ccifg1..2 1 63h 63h 63h 63h 63h 63h 63h 63h p1 1 50h 50h 50h 50h 50h 50h 50h 50h usci_a1 1 92h 92h 92h 92h 92h 92h 92h 92h usci_b1 1 93h 93h 93h 93h 93h 93h 93h 93h ta1.ccifg0 1 66h 66h 66h 66h 66h 66h 66h 66h ta1.ccifg1..2 1 67h 67h 67h 67h 67h 67h 67h 67h p2 1 51h 51h 51h 51h 51h 51h 51h 51h rtc_a 1 68h 68h 68h 68h 68h 68h 68h 68h delimiter 1 00h 00h 00h 00h 00h 00h 00h 00h table 6-63. msp430f551x device descriptor table (1) value size description address (bytes) f5519 f5517 f5515 f5514 f5513 info block info length 01a00h 1 55h 55h 55h 55h 55h crc length 01a01h 1 19h 17h 15h 14h 13h crc value 01a02h 2 per unit per unit per unit per unit per unit device id 01a04h 1 22h 21h 55h 55h 20h device id 01a05h 1 80h 80h 15h 14h 80h hardware revision 01a06h 1 per unit per unit per unit per unit per unit firmware revision 01a07h 1 per unit per unit per unit per unit per unit die record die record tag 01a08h 1 08h 08h 08h 08h 08h die record length 01a09h 1 0ah 0ah 0ah 0ah 0ah lot/wafer id 01a0ah 4 per unit per unit per unit per unit per unit die x position 01a0eh 2 per unit per unit per unit per unit per unit die y position 01a10h 2 per unit per unit per unit per unit per unit test results 01a12h 2 per unit per unit per unit per unit per unit adc12 calibration adc12 calibration tag 01a14h 1 05h 05h 11h 11h 05h adc12 calibration length 01a15h 1 10h 10h 10h 10h 10h adc gain factor 01a16h 2 blank blank blank blank blank (1) na = not applicable, blank = unused and reads ffh. copyright ? 2009 ? 2015, texas instruments incorporated detailed description 105 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-63. msp430f551x device descriptor table (1) (continued) value size description address (bytes) f5519 f5517 f5515 f5514 f5513 adc offset 01a18h 2 blank blank blank blank blank adc 1.5-v reference 01a1ah 2 blank blank blank blank blank temp. sensor 30 c adc 1.5-v reference 01a1ch 2 blank blank blank blank blank temp. sensor 85 c adc 2.0-v reference 01a1eh 2 blank blank blank blank blank temp. sensor 30 c adc 2.0-v reference 01a20h 2 blank blank blank blank blank temp. sensor 85 c adc 2.5-v reference 01a22h 2 blank blank blank blank blank temp. sensor 30 c adc 2.5-v reference 01a24h 2 blank blank blank blank blank temp. sensor 85 c ref calibration tag 01a26h 1 12h 12h 12h 12h 12h ref calibration ref calibration length 01a27h 1 06h 06h 06h 06h 06h ref 1.5-v reference 01a28h 2 per unit per unit per unit per unit per unit factor ref 2.0-v reference 01a2ah 2 per unit per unit per unit per unit per unit factor ref 2.5-v reference 01a2ch 2 per unit per unit per unit per unit per unit factor peripheral peripheral descriptor tag 01a2eh 1 02h 02h 02h 02h 02h descriptor peripheral descriptor 01a2fh 1 61h 63h 61h 5fh 5fh length 08h 08h 08h 08h 08h memory 1 2 8ah 8ah 8ah 8ah 8ah 0ch 0ch 0ch 0ch 0ch memory 2 2 86h 86h 86h 86h 86h 0eh 0eh 0eh 0eh 0eh memory 3 2 2ah 2ah 2ah 2ah 2ah 12h 12h 12h 12h 12h memory 4 2 2eh 2dh 2ch 2ch 2ch 22h 2ah 22h 22h 40h memory 5 2 96h 22h 94h 94h 92h 95h memory 6 1/2 n/a n/a n/a n/a 92h delimiter 1 00h 00h 00h 00h 00h peripheral count 1 20h 20h 20h 1fh 1fh 00h 00h 00h 00h 00h msp430cpuxv2 2 23h 23h 23h 23h 23h 00h 00h 00h 00h 00h jtag 2 09h 09h 09h 09h 09h 00h 00h 00h 00h 00h sbw 2 0fh 0fh 0fh 0fh 0fh 00h 00h 00h 00h 00h eem-l 2 05h 05h 05h 05h 05h 00h 00h 00h 00h 00h ti bsl 2 fch fch fch fch fch 10h 10h 10h 10h 10h sfr 2 41h 41h 41h 41h 41h 02h 02h 02h 02h 02h pmm 2 30h 30h 30h 30h 30h 02h 02h 02h 02h 02h fctl 2 38h 38h 38h 38h 38h 01h 01h 01h 01h 01h crc16 2 3ch 3ch 3ch 3ch 3ch 00h 00h 00h 00h 00h crc16_rb 2 3dh 3dh 3dh 3dh 3dh 00h 00h 00h 00h 00h ramctl 2 44h 44h 44h 44h 44h 106 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 table 6-63. msp430f551x device descriptor table (1) (continued) value size description address (bytes) f5519 f5517 f5515 f5514 f5513 00h 00h 00h 00h 00h wdt_a 2 40h 40h 40h 40h 40h 01h 01h 01h 01h 01h ucs 2 48h 48h 48h 48h 48h 02h 02h 02h 02h 02h sys 2 42h 42h 42h 42h 42h 03h 03h 03h 03h 03h ref 2 a0h a0h a0h a0h a0h 01h 01h 01h 01h 01h port mapping 2 10h 10h 10h 10h 10h 04h 04h 04h 04h 04h port 1/2 2 51h 51h 51h 51h 51h 02h 02h 02h 02h 02h port 3/4 2 52h 52h 52h 52h 52h 02h 02h 02h 02h 02h port 5/6 2 53h 53h 53h 53h 53h 02h 02h 02h port 7/8 2 n/a n/a 54h 54h 54h 0ch 0ch 0ch 0eh 0eh jtag 2 5fh 5fh 5fh 5fh 5fh 02h 02h 02h 02h 02h ta0 2 62h 62h 62h 62h 62h 04h 04h 04h 04h 04h ta1 2 61h 61h 61h 61h 61h 04h 04h 04h 04h 04h tb0 2 67h 67h 67h 67h 67h 04h 04h 04h 04h 04h ta2 2 61h 61h 61h 61h 61h 0ah 0ah 0ah 0ah 0ah rtc 2 68h 68h 68h 68h 68h 02h 02h 02h 02h 02h mpy32 2 85h 85h 85h 85h 85h 04h 04h 04h 04h 04h dma-3 2 47h 47h 47h 47h 47h 0ch 0ch 0ch 0ch 0ch usci_a/b 2 90h 90h 90h 90h 90h 04h 04h 04h 04h 04h usci_a/b 2 90h 90h 90h 90h 90h adc12_a 2 n/a n/a n/a n/a n/a 2ch 2ch 2ch 2ch 2ch comp_b 2 a8h a8h a8h a8h a8h 04h 04h 04h 04h 04h usb 2 98h 98h 98h 98h 98h interrupts comp_b 1 a8h a8h a8h a8h a8h tb0.ccifg0 1 64h 64h 64h 64h 64h tb0.ccifg1..6 1 65h 65h 65h 65h 65h wdtifg 1 40h 40h 40h 40h 40h usci_a0 1 90h 90h 90h 90h 90h usci_b0 1 91h 91h 91h 91h 91h adc12_a 1 01h 01h 01h 01h 01h ta0.ccifg0 1 60h 60h 60h 60h 60h ta0.ccifg1..4 1 61h 61h 61h 61h 61h usb 1 98h 98h 98h 98h 98h dma 1 46h 46h 46h 46h 46h ta1.ccifg0 1 62h 62h 62h 62h 62h ta1.ccifg1..2 1 63h 63h 63h 63h 63h p1 1 50h 50h 50h 50h 50h copyright ? 2009 ? 2015, texas instruments incorporated detailed description 107 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com table 6-63. msp430f551x device descriptor table (1) (continued) value size description address (bytes) f5519 f5517 f5515 f5514 f5513 usci_a1 1 92h 92h 92h 92h 92h usci_b1 1 93h 93h 93h 93h 93h ta1.ccifg0 1 66h 66h 66h 66h 66h ta1.ccifg1..2 1 67h 67h 67h 67h 67h p2 1 51h 51h 51h 51h 51h rtc_a 1 68h 68h 68h 68h 68h delimiter 1 00h 00h 00h 00h 00h 108 detailed description copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 7 device and documentation support 7.1 device support 7.1.1 getting started and next steps for an introduction to the msp430 ? family of devices and the tools and libraries that are available to help with your development, visit the getting started page . 7.1.2 development tools support all msp microcontrollers are supported by a wide variety of software and hardware development tools. tools are available from ti and various third parties. see them all at msp tools . 7.1.2.1 hardware features see the code composer studio for msp430 user's guide ( slau157 ) for details on the available features. break- range lpmx.5 msp430 4-wire 2-wire clock state trace points break- debugging architecture jtag jtag control sequencer buffer (n) points support msp430xv2 yes yes 8 yes yes yes yes no 7.1.2.2 recommended hardware options 7.1.2.2.1 target socket boards the target socket boards allow easy programming and debugging of the device using jtag. they also feature header pin outs for prototyping. target socket boards are orderable individually or as a kit with the jtag programmer and debugger included. the following table shows the compatible target boards and the supported packages. package target board and programmer bundle target board only 64-pin vqfn (rgc) msp-fet430u64usb msp-ts430rgc64usb 80-pin lqfp (pn) msp-fet430u80usb msp-ts430pn80usb 7.1.2.2.2 experimenter boards experimenter boards and evaluation kits are available for some msp devices. these kits feature additional hardware components and connectivity for full system evaluation and prototyping. see msp tools for details. 7.1.2.2.3 debugging and programming tools hardware programming and debugging tools are available from ti and from its third party suppliers. see the full list of available tools at msp tools . 7.1.2.2.4 production programmers the production programmers expedite loading firmware to devices by programming several devices simultaneously. part number pc port features provider program up to eight devices at a time. works with pc or as a stand- msp-gang serial and usb texas instruments alone package. copyright ? 2009 ? 2015, texas instruments incorporated device and documentation support 109 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 7.1.2.3 recommended software options 7.1.2.3.1 integrated development environments software development tools are available from ti or from third parties. open source solutions are also available. this device is supported by code composer studio ? ide (ccs). 7.1.2.3.2 mspware mspware is a collection of code examples, data sheets, and other design resources for all msp devices delivered in a convenient package. in addition to providing a complete collection of existing msp design resources, mspware also includes a high-level api called msp driver library. this library makes it easy to program msp hardware. mspware is available as a component of ccs or as a stand-alone package. 7.1.2.3.3 ti-rtos ti-rtos is an advanced real-time operating system for the msp microcontrollers. it features preemptive deterministic multi-tasking, hardware abstraction, memory management, and real-time analysis. ti-rtos is available free of charge and is provided with full source code. 7.1.2.3.4 msp430 usb developer ' s package msp430 usb developer ' s package is an easy-to-use usb stack implementation for the msp microcontrollers. 7.1.2.3.5 command-line programmer msp flasher is an open-source, shell-based interface for programming msp microcontrollers through a fet programmer or ez430 using jtag or spy-bi-wire (sbw) communication. msp430 flasher can be used to download binary files (.txt or .hex) files directly to the msp430 flash without the need for an ide. 7.1.3 device and development tool nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all msp430 mcu devices and support tools. each msp430 mcu commercial family member has one of three prefixes: msp, pms, or xms (for example, msp430f5438a). ti recommends two of three possible prefix designators for its support tools: msp and mspx. these prefixes represent evolutionary stages of product development from engineering prototypes (with xms for devices and mspx for tools) through fully qualified production devices and tools (with msp for devices and msp for tools). device development evolutionary flow: xms ? experimental device that is not necessarily representative of the electrical specifications for the final device pms ? final silicon die that conforms to the electrical specifications for the device but has not completed quality and reliability verification msp ? fully qualified production device support tool development evolutionary flow: mspx ? development-support product that has not yet completed ti's internal qualification testing. msp ? fully-qualified development-support product xms and pms devices and mspx development-support tools are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." 110 device and documentation support copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 msp devices and msp development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (xms and pms) have a greater failure rate than the standard production devices. ti recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. ti device nomenclature also includes a suffix with the device family name. this suffix indicates the package type (for example, pzp) and temperature range (for example, t). figure 7-1 provides a legend for reading the complete device name for any family member. figure 7-1. device nomenclature copyright ? 2009 ? 2015, texas instruments incorporated device and documentation support 111 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513 processor family cc = embedded rf radio msp = mixed-signal processor xms = experimental silicon pms = prototype device 430 mcu platform tis low-power microcontroller platform device type memory type c = romf = flash fr = fram g = flash or fram (value line) l = no nonvolatile memory specialized application afe = analog front end bt = preprogrammed with bq = contactless power cg = rom medical fe = flash energy meter fg = flash medical fw = flash electronic flow meter bluetooth series 1 series = up to 8 mhz2 series = up to 16 mhz 3 series = legacy 4 series = up to 16 mhz with lcd 5 series = up to 25 mhz6 series = up to 25 mhz with lcd 0 = low-voltage series feature set various levels of integration within a series optional: a = revision n/a optional: temperature range s = 0c to 50 c c to 70 c i = 40 c to 85 c t = C40 c to 105 c c = 0 C packaging http://www.ti.com/packaging optional: tape and reel t = small reel r = large reel no markings = tube or tray optional: additional features -ep = enhanced product ( 40c to 105c) -ht = extreme temperature parts ( 55c to 150c) -q1 = automotive q100 qualified C C msp 430 f 5 438 a i zqw t -ep processor family series optional: temperature range 430 mcu platform packaging device type optional: a = revision optional: tape and reel feature set optional: additional features
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 7.2 documentation support the following documents describe the msp430f552x and msp430f551x devices. copies of these documents are available on the internet at www.ti.com . slau208 msp430x5xx and msp430x6xx family user's guide. detailed information on the modules and peripherals available in this device family. slaz314 msp430f5529 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz313 msp430f5528 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz312 msp430f5527 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz311 msp430f5526 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz310 msp430f5525 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz309 msp430f5524 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz308 msp430f5522 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz307 msp430f5521 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz306 msp430f5519 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz305 msp430f5517 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz304 msp430f5515 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz303 msp430f5514 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. slaz302 msp430f5513 device erratasheet. describes the known exceptions to the functional specifications for all silicon revisions of the device. 112 device and documentation support copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 www.ti.com slas590m ? march 2009 ? revised november 2015 7.3 related links table 7-1 lists quick access links. categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. table 7-1. related links technical tools & support & parts product folder sample & buy documents software community msp430f5529 click here click here click here click here click here msp430f5528 click here click here click here click here click here msp430f5527 click here click here click here click here click here msp430f5526 click here click here click here click here click here msp430f5525 click here click here click here click here click here msp430f5524 click here click here click here click here click here msp430f5522 click here click here click here click here click here msp430f5521 click here click here click here click here click here msp430f5519 click here click here click here click here click here msp430f5517 click here click here click here click here click here msp430f5515 click here click here click here click here click here msp430f5514 click here click here click here click here click here msp430f5513 click here click here click here click here click here 7.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? community ti's engineer-to-engineer (e2e) community . created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki . established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 7.5 trademarks msp430, microstar junior, code composer studio, e2e are trademarks of texas instruments. 7.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 7.7 glossary ti glossary this glossary lists and explains terms, acronyms, and definitions. copyright ? 2009 ? 2015, texas instruments incorporated device and documentation support 113 submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
msp430f5529 , msp430f5528 , msp430f5527 , msp430f5526 msp430f5525 , msp430f5524 , msp430f5522 , msp430f5521 msp430f5519 , msp430f5517 , msp430f5515 , msp430f5514 , msp430f5513 slas590m ? march 2009 ? revised november 2015 www.ti.com 8 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 114 mechanical, packaging, and orderable information copyright ? 2009 ? 2015, texas instruments incorporated submit documentation feedback product folder links: msp430f5529 msp430f5528 msp430f5527 msp430f5526 msp430f5525 msp430f5524 msp430f5522 msp430f5521 msp430f5519 msp430f5517 msp430f5515 msp430f5514 msp430f5513
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples asp00886irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5522 asp00886irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5522 msp430a132irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5528 msp430a133irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5526 msp430a134irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5524 msp430a145irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5522 msp430a147izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5522 msp430f5513irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5513 msp430f5513izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5513 msp430f5513izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5513 msp430f5514irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5514 msp430f5514irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5514 msp430f5514izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5514 msp430f5514izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5514 msp430f5515ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5515
package option addendum www.ti.com 15-apr-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples MSP430F5515IPNR active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5515 msp430f5517ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5517 msp430f5517ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5517 msp430f5519ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5519 msp430f5519ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5519 msp430f5521ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5521 msp430f5521ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5521 msp430f5522irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5522 msp430f5522irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5522 msp430f5522izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5522 msp430f5522izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5522 msp430f5524irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5524 msp430f5524irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5524 msp430f5524iyffr active dsbga yff 64 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim m430f5524 msp430f5524izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5524 msp430f5524izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5524
package option addendum www.ti.com 15-apr-2017 addendum-page 3 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples msp430f5525ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5525 msp430f5525ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5525 msp430f5526irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5526 msp430f5526irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5526 msp430f5526iyffr active dsbga yff 64 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim m430f5526 msp430f5526izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5526 msp430f5526izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5526 msp430f5527ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5527 msp430f5527ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5527 msp430f5528irgcr active vqfn rgc 64 2000 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5528 msp430f5528irgct active vqfn rgc 64 250 green (rohs & no sb/br) cu nipdau | cu nipdauag level-3-260c-168 hr -40 to 85 m430f5528 msp430f5528iyffr active dsbga yff 64 2500 green (rohs & no sb/br) snagcu level-1-260c-unlim -40 to 85 m430f5528 msp430f5528izqe active bga microstar junior zqe 80 360 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5528 msp430f5528izqer active bga microstar junior zqe 80 2500 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 85 m430f5528 msp430f5529ipn active lqfp pn 80 119 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5529 msp430f5529ipnr active lqfp pn 80 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 m430f5529
package option addendum www.ti.com 15-apr-2017 addendum-page 4 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430f5513irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5513izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 msp430f5514irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5514izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 MSP430F5515IPNR lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5517ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5519ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5521ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5522irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5522izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 msp430f5524irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5524iyffr dsbga yff 64 2500 330.0 12.4 3.86 3.86 0.69 8.0 12.0 q2 package materials information www.ti.com 18-nov-2016 pack materials-page 1
device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant msp430f5524izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 msp430f5525ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5526irgcr vqfn rgc 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5526irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5526iyffr dsbga yff 64 2500 330.0 12.4 3.86 3.86 0.69 8.0 12.0 q2 msp430f5526izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 msp430f5527ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 msp430f5528irgct vqfn rgc 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 q2 msp430f5528iyffr dsbga yff 64 2500 330.0 12.4 3.86 3.86 0.69 8.0 12.0 q2 msp430f5528izqer bga mi crosta r juni or zqe 80 2500 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q1 msp430f5529ipnr lqfp pn 80 1000 330.0 24.4 15.0 15.0 2.1 20.0 24.0 q2 *all dimensions are nominal package materials information www.ti.com 18-nov-2016 pack materials-page 2
device package type package drawing pins spq length (mm) width (mm) height (mm) msp430f5513irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430f5513izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 msp430f5514irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430f5514izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 MSP430F5515IPNR lqfp pn 80 1000 367.0 367.0 45.0 msp430f5517ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430f5519ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430f5521ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430f5522irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430f5522izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 msp430f5524irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430f5524iyffr dsbga yff 64 2500 367.0 367.0 35.0 msp430f5524izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 msp430f5525ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430f5526irgcr vqfn rgc 64 2000 367.0 367.0 38.0 msp430f5526irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430f5526iyffr dsbga yff 64 2500 367.0 367.0 35.0 msp430f5526izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 msp430f5527ipnr lqfp pn 80 1000 367.0 367.0 45.0 msp430f5528irgct vqfn rgc 64 250 210.0 185.0 35.0 msp430f5528iyffr dsbga yff 64 2500 367.0 367.0 35.0 msp430f5528izqer bga microstar junior zqe 80 2500 336.6 336.6 28.6 msp430f5529ipnr lqfp pn 80 1000 367.0 367.0 45.0 package materials information www.ti.com 18-nov-2016 pack materials-page 3
mechanical data mtqf010a january 1995 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pn (s-pqfp-g80) plastic quad flatpack 4040135 / b 11/96 0,17 0,27 0,13 nom 40 21 0,25 0,45 0,75 0,05 min seating plane gage plane 41 60 61 80 20 sq sq 1 13,80 14,20 12,20 9,50 typ 11,80 1,45 1,35 1,60 max 0,08 0,50 m 0,08 0 7 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
d: max = e: max = 3.79 mm, min = 3.79 mm, min = 3.73 mm3.73 mm

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